Understanding The Ivy Bridge Architecture

The development of emerging technology is a race. Development takes time. The new generation of embedded components then needs more time before it’s widely accepted in the industry. Of course, the manufacturer is challenged to keep costs in check while this whole process rolls out.

A look at the industry today draws attention to Ivy Bridge, the third-generation Core processor from Intel (Fig. 1). It’s the newest processor on the market. Owing to its highly attractive feature set, it’s also an ideal candidate for building sophisticated embedded applications. But such leaps in innovation increase the pressure on engineers to keep pace with their implementation.

1. Ivy Bridge is Intel’s third-generation Core processor series.

Ivy Bridge is a good case history, since its improvements in performance, architecture, interface, power savings, graphics definition, and security are rendering it easier for embedded systems manufacturers to advance their own designs and meet the tightening requirements of their markets. As designers take advantage of this technology, processor and systems engineers work together to collectively drive the embedded industry forward.

Improved Chip Architecture

With the introduction of the 32-nm process in 2009, Intel maintained its historical doubling of chip functionality every two years by continually reducing transistor dimensions. But as gate lengths went to less than 32 nm, it became more challenging to overcome the fundamental physical limitations imposed by traditional semiconductor materials.

As the size decreased, planar transistors increasingly suffered from the undesirable off-state leakage current, which increased the idle power required by the device. To solve this issue, a radical change in design was needed. With Ivy Bridge chips, Intel has introduced the 22-nm process and the tri-gate transistor (Fig. 2), which, for the first time in history, will bring silicon transistors into the “3D” realm.

2. Intel introduced the tri-gate transistor with the 22-nm process used on Ivy Bridge.

Die shrinks result in power improvements and power savings because the manufacturer can use the new process to squeeze more circuits onto a silicon chip that’s the same size as those using the earlier process node. Adding a third dimension to the transistor allows Intel to further increase the density to 1.4 billion transistors on a die size of 160 mm² and insert more capabilities into every square millimeter of the processors.

The current flow is then controlled on three sides of the channel (top, left, and right) rather than just from the top, as in conventional, planar transistors (Fig. 3). The net result is much better control of the transistor, a maximization of current flow for when high performance is required, and minimization when it is off to reduce leakage.

Three-dimensional tri-gate transistors form conducting channels on three sides of a vertical fin structure to maximize current flow on the one hand and reduce leakage current at the other hand. Moreover, tri-gate transistors can have multiple vertical fins connected together to increase total drive strength for higher performance.

Enhanced Power Performance

Due to Ivy Bridge’s 22-nm shrink and the transistor redesign, which maximizes current flow, Ivy Bridge processors are showing up to 20% enhanced computing power and up to 40% increased performance per watt compared to designs based on second-generation Intel Core processors like Westmere. This increase in power efficiency offers more flexibility in setting a system’s thermal envelope, allowing applications with tight thermal constraints to take advantage of the parallel performance of up to four CPU cores and eight threads.

This way, users get high efficiency in small form-factor applications. Due to the increased level of integration (multi-core, higher performance architecture), they also can accomplish unprecedented consolidation of multiple computing systems on one platform.

A new level of virtualization results in reduced hardware costs, as one multicore system is less expensive than several single-core systems. The decreased system count also results in higher mean time before failure (MTBF) values for the consolidated installation and helps to save valuable space for size, weight, and power (SWaP) optimized high-performance embedded computing.

Better Turbo Boost

An enhanced Intel Turbo Boost 2.0 Technology in Ivy Bridge accommodates embedded systems that end up in military or other power-hungry applications and need to be extra responsive and able to perform in critical, last minute situations. It was introduced with the previous generation Intel Core processors, but this time around, it behaves with optimum efficiency.

Turbo Boost mode increases the clock speeds of both the processor cores and the graphics unit independently. Processor cores and processor graphics resources then automatically shift to accelerate performance, tailoring a workload to give users an immediate performance boost for their applications whenever needed. Depending on the load, the actual speed can be increased by up to 40%.

Because Intel’s turbo boost can overclock all cores, not just single ones, both old single-threaded applications and modern multi-threaded applications benefit from the boost. Furthermore, the Power Manager now has the option of overclocking a core that was switched off.

Right after the core wakes up, the maximum application performance is available to reactivate inactive processes at high speed as needed. Thus, the thermal budget is more efficiently used. Also, Intel Turbo Boost 2.0 will now increase processor performance beyond the specified electrical thermal design power (TDP) for a short time, without crossing the thermal limit, maximizing the usability of turbo boost.

Extended AVX And SEE Instructions

Expanding on the implementation of the double-width Advanced Vector Extensions (AVX) that were introduced with the previous Generation Intel Core processors (see “Intel’s AVX Scales To 1024-Bit Vector Math”), Ivy Bridge processors bring two new Float16 format conversion instructions (VCVTPH2PS and VCVTPS2PH) into play.

These instructions support the conversion between the 16-bit (compressed) floating-point memory format and the 32-bit single precision formats (either 256-bit AVX or 128-bit SSE), allowing a higher dynamic range in the same memory footprint. By being able to convert the standard 16-bit compressed floating-point number into either 256-bit AVX or 128-bit SSE, number calculations using these extended floating-point numbers will be significantly more accurate.

In previous processors, the functionality of these instructions involved multiple steps, adding time to operations. The new AVX and SSE instruction sets accelerate floating-point intensive applications in high-performance embedded computing as well as the digital processing of images, videos, and audio data in industrial automation, medical, and military applications, suiting embedded platforms equipped with the Ivy Bridge processor especially to situations where large amounts of data have to be processed in a limited thermal envelope.

Improved Peripheral Interface

Due to the requirements for faster interfaces, further performance improvements have been achieved in Ivy Bridge. The memory controller now supports 1600 MHz to connect to DDR3-1600 memory, which meets the high-speed system requirements, for example, of telecommunication applications. The same is true for the processor’s 16 PCI Express 3.0 lanes.

PCI Express 3.0 is the next evolution of the general-purpose PCI Express I/O standard, providing a transfer rate of up to 8 Gtransfers/s. Thus, the interconnect performance bandwidth is doubled over PCI Express 2.0, while preserving compatibility with software and mechanical interfaces.

The latest high-end graphics will utilize this additional bandwidth. It also will be used to connect with 10-Gbit/s and 40-Gbit/s Ethernet chips in telecommunications as well as high-speed solid-state drives. Any application, then, can excel through faster response times when it’s accessing the hard drive. Additionally, high-bandwidth VPX applications with PCI Express-based intra-communication via the backplane benefit from the doubled transfer rates, enabling high bandwidth on the data plane.

The accompanying Intel 7-Series chipsets directly integrate support for four high-speed USB 3.0 interfaces without the need for additional controller chips, as was the case for the previous generation of processors. This allows for fast file transfers and device synchronization. It also enables the connection of the most modern peripheral components such as full HD video cameras or fast external storage media.

Additional Power Savings

In addition to realizing performance gains, Ivy Bridge processors save power via support for low-voltage DDR3 (DDR3L), options for low system operating voltages in ultra-low-power parts, and DDR3 power gating, which enables parts of the memory interface to be disabled when in deep C-states.

All Ivy Bridge processors feature power-aware interrupt routing (PAIR) to improve Intel’s core sleeping technology by making the CPU aware of which of its cores are asleep and which are awake. It can then send interrupt requests from peripherals or a software application to cores that are up and running, rather than waking a core that has been powered down to handle the interrupt.

The system agent was introduced in the previous generation and refers to the display output, memory controller, and DMI and PCI Express interfaces on the processor. The System Agent operates on a voltage plane separate from the rest of the chip, which in turn helps power optimize those interfaces.

Enhanced On-Chip Graphics

Besides architectural and power enhancements, the Ivy Bridge’s designers needed to deliver a significantly improved integrated graphics unit because so many embedded systems involve high-resolution graphics as part of their operation. The Intel HD Graphics 4000 can produce up to twice the 3D graphics performance of the previous processor, bringing richer details at higher resolutions.

Just like the main processor, the Intel HD Graphics 4000 has multiple cores, along with DirectX 11 and OpenGL 3.1 (Shader Model 5) support. Intel calls the cores “Execution Units” (EUs), while other manufacturers call them GPUs. Each EU can execute graphics instructions. Previous generations only had six to 12 of these units. The current one has up to 16. When you double the cores, you double the performance.

The EUs also suit general-purpose computations via OpenCL 1.1 and Direct Compute 11.0. They’re backed by an increased local shared memory (L3 cache), enabling a more efficient exchange of data between the units. With its support of three independent displays, the Ivy Bridge processor graphics perform well in multi-screen applications without an additional dedicated graphics controller.

Built-in visual features mean 50% better performance over previous versions. For example, Intel Quick Sync Video 2.0 uses dedicated hardware instead of software to accelerate media processing functions such as video encode, decode, and transcode operations. Intel Clear Video HD integrates multiple hardware and software image processing technologies to enable jitter-free, 1080p playback with enhanced color fidelity, enabling an improved user experience.

Secure Manageability

Designs based on the Ivy Bridge processor have improved security with new features such as Intel Secure Key, which protects data and assets with more safety through encryption, and Intel OS Guard, which helps detect and prevent malware.

Intel Secure Key consists of a digital random number generator that creates truly random numbers to strengthen encryption algorithms. Intel OS Guard, or Supervisor Mode Execution Protection (SMEP), provides an additional level of system protection by blocking malicious software attacks from user mode code when the system is running in the highest privilege level. This helps defend against privilege escalation attacks where a hacker tries to remotely take over another person’s system.

Intel Secure Key and Intel OS Guard join existing platform security features such as Intel Identity Protection Technology (Intel IPT) and Intel Anti-Theft technology (Intel AT) to help make these platforms some of the most secure in the industry. When paired with the Intel Series 7 chipset, new designs with Intel IPT can make a portion of the screen unreadable to spyware with the “protected transaction display” feature, helping prevent a hacker from obtaining login credentials that could lead to identity theft.

Continued support for Intel vPro and Intel AMT 8.0 technology enables secure data exchange among increasingly connected devices across various industries and allows for problems to be diagnosed, managed, and repaired remotely, which can make many onsite service visits unnecessary.

The new processor generation furthermore introduces a software visible random number generation mechanism supported by a high-quality entropy source. This capability is made available to programmers through the new RDRAND instruction.

The resultant random number generation capability is designed to comply with existing industry standards in this regard (ANSI X9.82 and NIST SP 800-90). Some possible usages of the new RDRAND instruction include cryptographic key generation as used in a variety of applications including communication, digital signatures, and secure storage. These security features are a great enhancement to hardware platforms and are a must in a world where ever more devices are connected.

With its decidedly improved performance, expanded I/O, increased efficiency, and sharp graphics capabilities, leading embedded systems manufacturers already are specifying Ivy Bridge, and they are re-engineering to meet its footprint and operating parameters. New product introductions built around the Intel Core Ivy Bridge are anticipated from General Micro Systems, Congatec, Extreme Engineering Solutions, and other companies.

If the new processors follow a typical replacement cycle, Ivy Bridge would overtake its predecessors in about 18 months from introduction. That means that by fall 2013, the water may well be under the Sandy Bridge.