You can now get your hands on Altera's 28nm Arria V and Cyclone V with hard core Arm Cortex-A9 cores announced awhile ago (see Dual Core Cortex-A9 With ECC Finds FPGA Home). These chips take on Xilinx's Zynq-7000 EPP chips (see FPGA Packs In Dual Cortex-A9 Micro).
Altera's new hardware offering is significant but it is the software that is likely to make more difference in the long run. This is coming in the form of Arm's Development Studio 5 (DS-5) Altera Edition tookit that supports features like cross triggering (Fig. 1).
Figure 1. The new debug support handles cross triggering between logic in the FPGA fabric and software running on the hard core processors.
New FPGA projects typically incorporate at least one processor core making the new Altera chips with dual Cortex-A9's very interesting. This also means that software development is a significant portion of an embedded solution. Integrating the hardware and software sides has not been an easy task in the past especially when it comes to debugging. This is where DS-5 shines.
Debugging FPGA with processors usually requires a JTAG interface, like Altera USB Blaster, for the FPGA and another for the processors, like Arm's DStream (Fig. 2). In the past, separate debug applications were used with each JTAG interface. The person in the middle was responsible for coordinating information between the two applications. DS-5 allows developers to utilize both debug hardware interfaces at the same time.
Figure 2. Debugging software integrated with FPGA hardware often requires two interface cables.
This duality would not be much of an issue if it where not for the usefulness of the information from both sides of the coin. Alteta's tools provide real time, logic analyzer functionality to the innards of the FPGA fabric allowing developers to visualize the hardware's operation. Software development tools like Arm's DS-5 provide insight into the software running on the processors. Features like cross triggering allow the two sides to come together. Cross triggering allows an event in the FPGA fabric to do things like initiate a software breakpoint. This can significantly simplify debugging because often the software application is utilizing the FPGA hardware but the possible asynchronous nature of the connection between the two can make software side-only debugging a challenge.
Stop-mode debugging is just part of the DS-5 mix. It also allows non-intrusive capture and visualization of signal events in the FPGA fabric. This hardware trace information as well as software trace information is time stamped so that time-correlated event and be matched to processor instruction trace. This provides a developer insight that was unavailable before.
The DS-5 Streamline performance analyzer is similar but it correlates software thread and event information using hardware counters. These counters are in the SoC and can be incorporated into the FPGA fabric. The performance analyzer can be used to identify system-level bottlenecks.
DS-5 has been integrated with the FPGA development tools as well. One aspect of hardware/software design is the registers that exist in the FPGA fabric. These are defined using the FPGA development tools but must be utilized by the software development tools. This is minimally a C header file with the register definitions. DS-5 takes the definitions from Altera's tools and provides users with access to these registers in the debugger (Fig. 3).
Figure 3. DS-5 provides unified FPGA-adaptive view of FPGA registers accessible by software.
The register definitions down to the bit level are available in the debugger. This allows the debugger to change a bit when a user needs this capability.
The ARM DS-5 Altera Edition toolkit will be included in the Altera SoC Embedded Design Suite (Altera SoC EDS) Subscription Edition for $995.
