As you might expect from the conference that brings together the players of the industry that makes the chips that run the electronic devices we all use in our daily lives, there was plenty of innovation and intellectual energy to go around. Several themes surfaced at the 49th Design Automation Conference, among them the move to a new node—20 nm; the move to a new structure—3D ICs; the move to a new wafer technology to make chips ever more energy efficient—FD-SOI; and the development of ever faster tools to deal with ever more complex chips.
On the 20 nm front, Cadence Design Systems announced just prior to DAC that it had contributed to STMicroelectronics tapeout of a 20-nanometer test chip that incorporated both custom analog and digital methodologies in a mixed-signal SoC. Cadence said that engineers from the two companies collaborated closely to develop technologies and deploy methodologies. They used the Cadence Encounter and Virtuoso platforms to enable design, implementation and signoff.
In addition, Cadence announced that it has collaborated with Samsung Electronics to deliver a 20-nanometer design methodology that incorporates double patterning technology for joint customer deployment and internal test chips. The collaboration between Cadence and Samsung brings new process advances for mobile consumer electronics, enabling not only design at 20 nanometers but future process nodes as well.
Cadence was also at the forefront with 3D-ICs, announcing a collaboration with TSMC on 3D-IC design infrastructure development. TSMC and Cadence teams worked together to create and integrate features to support this new type of design, culminating in the test-chip tapeout of TSMC’s first heterogeneous CoWoS (Chip-on-Wafer-on-Substrate) part. CoWoS is an integrated process technology that bonds multiple chips in a single device to reduce power, improve system performance and reduce form factor.
Cadence 3D-IC technology fosters multi-chip co-design between digital, custom and package environments, incorporating through-silicon vias (TSVs) on both chips and silicon carriers. It also supports micro-bump alignment, placement, routing and design for test. Included are key 3D-IC design IP, such as a Wide IO controller and PHY to support Wide IO memories. Test modules were created using the Cadence Encounter RTL-to-GDSII flow, Virtuoso custom/analog flow, and Allegro system-in-package solutions. For more about 3D ICs, see the whitepaper “3D ICs with TSVs—Design Challenges and Requirements.”
On the low-power front, Horacio Mendez, Executive Director of the SOI Industry Consortium, was at DAC to talk about the low power implications of FP-SOI (Fully Depleted Silicon On Insulator). Then immediately following the conference, STMicroelectronics announced that it would be working with GlobalFoundries to mass produce a new generation of semiconductors on ST’s FD-SOI technology. The company says that chips with FD-SOI technology offer optimal performance and draw 35 percent less power than similar chips made from traditional materials. Furthermore, ST indicated that it plans to open access to its FD-SOI technology to GlobalFoundries’ other customers. This news ultimately means that the industry could eventually see FD-SOI chips from a variety of semiconductor designers around the world. For more information on FD-SOI technology, visit the SOI Industry Consortium’s web site.
Calypto Design Systems also strummed the low-power chord at DAC with its introduction of Catapult Low Power. The company says that this is the industry’s first production quality, high-level synthesis tool that adds power as an optimization goal. By leveraging Calypto’s power analysis and optimization technology, Catapult LP provides a closed loop optimization across power, performance and area (PPA) to address the challenges of power-aware design. Catapult LP, which takes advantage of Calypto’s PowerPro technology, strives to optimize designs at the architecture level where 80% of power decisions are made. Commenting on the new tool, Shawn McCloud, Vice President of Marketing at Calypto referenced the 2011 merger of Catapult and Calypto Design Systems and said, “Combining Catapult with Calypto’s PowerPro technology ‘under the hood’ demonstrates why the merger is good for our customers.”
In another power related announcement, Docea Power, a company that makes ESL (Electronic System Level) software tools for power and thermal analysis and modelling, said that it is shipping Aceplorer 3.0 and also announced AceThermalModeler 1.1. Aceplorer models and optimizes electronic design power and thermal consumption for early architecture exploration, architecture validation and power budget tracking during electronic design implementation stages. AceThermalModeler creates compact RC thermal models for complete systems from system on chips to system-in-packages, 3D ICs to complete boards.
Aceplorer 3.0's new features include an event scheduler and support for thermal models created with AceThermalModeler. AceThermalModeler 1.1's new features include an enhanced graphical user interface (GUI) with capabilities for 3D and thermal model creation and debugging.
Moving now to the topic of speed, an interesting new tool was introduced by a company called Flexras Technologies. Flexras specializes in partitioning for FPGA-based prototyping. Its new tool, the Wasga Compiler, is the first timing-driven, multi-FPGA partitioning software for ASIC and SoC prototyping. According to CEO, Hayder Mrabet, the Wasga Compiler complements FPGA-based SoC prototyping with high-performance automatic partitioning.
“Engineers benefit from high clock frequencies, fast execution time and unlimited design capacity. Existing tools notoriously fail the complex partitioning challenge,” Hrabek said.
The Wasga compiler automatically partitions large designs onto multiple FPGAs while addressing chip resources, connectivity and the clock frequency constraints required for running software applications in near real time. The compiler typically delivers a 10X clock frequency increase, handles multi-billion ASIC gates equivalent designs, and maps them to any Altera or Xilinx board, whether off-the-shelf or custom.
A tool that got a speed upgrade was Atrenta’s SpyGlass RTL analysis and optimization platform. The company announced the availability of a Fast Lint methodology for the platform. Tests on a wide range of designs have shown a 4X to 9X speed improvement, while still delivering accurate, low noise results.
In addition to Fast Lint, the company demonstrated hierarchical analysis support, which it says can deliver 5X to over an order-of-magnitude speed improvement for highly complex designs as compared to running flat—that is, without hierarchy.
Also upgrading its lint tool was Real Intent. The company announced the release of version 1.5.1 of its Ascent Lint tool. This version brings greater ease of use and even faster turnaround time than the previous version. The company also said that re-invoking lint analysis from the debugger GUI is dramatically faster with shorter turnaround times.
Not content with an upgraded linter, Real Intent also announced the release of version 4.1 of it Meridian Clock Domain Crossing (CDC) analyzer. The analyzer has a new formal engine that goes further and faster to find hidden CDC problems in SoC designs.
Speed was also at the heart of Tanner EDA’s announcement of the Tanner Analog FastSPICE solution. This add-on to the company’s front end and full flow analog/mixed-signal design suites brings Berkeley Design Automation’s Analog FastSPICE platform to Tanner EDA customers. Tanner says it delivers foundry-certified nanometer SPICE accuracy at speeds 5x to 10x faster than any other simulator on a single core and an additional 2x to 4x performance uptick with multithreading.
A new entrant into the EDA space—which had its coming out party at DAC—is the brainchild of an Australian named Sam Appleton. He said that his company, Ausdia, was literally started in a garage in 2006 by him and another engineer. Their new tool is called Timevision. It is a solution for timing constraints development and verification, and is suited for team members at the RTL, STA/synthesis, and implementation stages. Appleton calls it a next- generation tool that takes full advantage of modern multicore computers.
Timevision supports designs up to 200M instances, and constraint verification, even on a large design, is typically less than one hour. For example, a 5M instance, 120 clock design runtime on a 4-core server is around 45 minutes. Also, Timevision runtimes are claimed to be 5X to 10X faster than STA tools for constraint checking. A full explanation of Timevision and the technology behind it can be found on Ausdia’s web site.
Other DAC News
In a selection of other DAC news, the OCP-IP (Open Core Protocol International Partnership) organization had several announcements. As its name suggests, OCP-IP is dedicated to proliferating a common standard for intellectual property (IP) core interfaces, or sockets, that facilitate "plug and play" system-on-chip design. One of the announcements indicated that the new OCP 3.1 specification had entered member review. The new spec adds several important capabilities, which are listed on the OCP-IP web site. The new features essentially allow engineers to leverage OCP to ensure IP reuse on the world’s most advanced leading-edge designs regardless of chip architecture or which processor cores are featured.
OCP-IP also released a new Compliance Document into member review, a newly updated version of its Transaction Generator tool, and new SystemC TLM Kits (Transaction Level Models). With regards to the latter, the work by OCP-IP’s System Level Design Working Group ensures continued alignment with the Accellera Systems Initiative SystemC TLM-2 standard and is the most advanced TLM-2 based, industry-ready kit in existence today.
Finally, OCP-IP announced a new book entitled “Introduction to Open Core Protocol: Fastpath to System on Chip Design.” The book provides a hands-on, how-to guide for semiconductor design.
Last on the list, but certainly not least, was Synopsys announcement of the industry's first integrated hybrid prototyping solution. It combines Synopsys' Virtualizer virtual prototyping and Synopsys' HAPS FPGA-based prototyping tools to accelerate the development of system-on-chip hardware and software. By using Virtualizer virtual prototyping for new design functions and HAPS FPGA-based prototyping for reused logic, Synopsys says designers can start software development up to 12 months earlier in the design cycle. In addition, designers are able to accelerate hardware/software integration and system validation, significantly reducing the overall product design cycle. For instance, with high-performance models for ARM Cortex processors, ARM AMBA protocol-based transactors, and DesignWare IP, developers can easily partition their ARM processor-based designs into virtual and FPGA-based prototypes as best suited to their design requirements.
Hybrid prototyping also enhances software stack validation through very high-speed execution of processors using a Virtualizer virtual prototype. It allows direct connection to real-world I/O model interfaces through analog PHYs or test equipment attached to a HAPS FPGA-based prototype. In addition, designers can take advantage of existing RTL or IP in the FPGA-based prototype and new functions in SystemC transaction-level models, which are faster to implement and available much sooner in a project lifecycle.
Synopsys' high-performance HAPS UMRBus (Universal Multi-Resource Bus) physical link efficiently transfers data between the virtual and FPGA-based prototyping environments.
“Hybrid prototyping offers design teams the best of what both hardware and software prototyping have to offer,” said John Koeter, vice president of marketing for IP and systems at Synopsys. "By integrating the strengths of Virtualizer virtual prototyping with HAPS FPGA-based prototyping using the UMRBus physical link, Synopsys enables designers to develop fully operational SoC prototypes much faster and earlier in the design cycle, and accelerate software development and full system validation."