With as many as 40% of ASIC and ASSP designers doing FPGA prototyping, Synopsys decided to spin a version of its Design Compiler (DC) synthesis tool for FPGA designers. The new tool, dubbed DC FPGA, aims squarely at designers doing prototype work on today's high-end FPGAs.
Prototyping is most effective when manual changes between the FPGA and ASIC implementations are kept to a minimum. DC FPGA is based on the existing Design Compiler synthesis tool used by many designers when migrating FPGA prototypes to an ASIC implementation, eliminating lots of those manual changes between flows. Thus, designers can sidestep the traditional process of designing once for the FPGA prototype and then substantially overhauling their RTL for subsequent ASIC implementation.
In addition to optimizing Design Compiler for FPGAs, Synopsys added what it's calling Adaptive Optimization Technology (AOT). AOT searches among the various synthesis algorithms programmed into the tool to find the ones that offer the best performance for a given circuit. It applies only those algorithms, reordering them if necessary to achieve the best possible results. Not only are runtimes reduced, but the tool also delivers average timing improvements of 15% after placement and routing.
Designers stand to reap further design improvements from the availability of other ASIC tools, such as Formality equivalence checking, LEDA RTL checking, PrimeTime static timing analysis, and Synopsys' DesignWare IP libraries.
A standalone license for Design Compiler FPGA starts at $36,750 for a one-year technology subscription. Existing DC users can buy an add-on DC FPGA license for $19,600.
Synopsys Inc. www.synopsys.com