Fast-Turn ASIC Platform Delivers ASIC Performance With FPGA Flexibility

Although a full ASIC design usually results in delivering the smallest chip and best performance, it is often the most time-consuming and most expensive approach to select unless the volume will be large enough to offset the nonrecurring development costs. In today’s fast moving market, the time-to-market pressures and cost issues often force companies to explore FPGA and other lower-cost alternatives.

The just-released AccelArray developed by Fujitsu Microelectronics has been targeted to address just such turnaround and cost issues. Requiring just three metal layers to customize the on-chip logic, the AccelArrays incorporate many pre-diffused features and blocks of logic that will help speed the design without compromising performance (see photo).

Fabricated using 0.11-mm design rules, the arrays deliver performance levels similar to that of ASICs, but have non-recurring engineering costs about 80% less than cell-based designs using the same design rules, and deliver more than three times the performance of high-end FPGAs at about 10% of their cost. To do all that, engineers at Fujitsu embedded many predefined resources in the AccelArray chips.

The first AccelArray implementations will include pre-diffused blocks of SRAM (860 k to 4.6 Mbits), analog phase-locked loops, a global clock tree, and logic blocks that include uncommitted gates (512 to 3842 kgates), embedded flip-flops (23 to 173 k flip-flops), and register files. Metal-mask configurable I/O cells (472 to 1128) provide a wide range of interface options, including HSTL, LVCMOS, PCML, LVDS (622 Mbits/s), SSTL-2, PCI-66, and PCI-X. Custom logic can also be configured in the logic array portion of the chip. That logic can be implemented using the company’s logic libraries that have been optimized for high-density or high performance.

A typical design cycle with AccelArray might consume about two to four weeks for the physical design, and another two to four weeks for tape out and prototype manufacturing. In contrast, a full ASIC design might require a total of 28 weeks for the same functions. In addition to speeding the design side, the AccelArrays also deal with signal integrity issues and testability by incorporating design approaches to avoid crosstalk and improve testability. Pricing is negotiated based on platform size, package, and design support required.