Toshiba and Western Digital Reveal Thickest 3D NAND, But No Word on Cost Yet
Less than two years ago, memory chipmaker Toshiba demolished one of its major NAND manufacturing plants in Yokkaichi, Japan, and built an entirely new facility on the site. Now the facility, filled with new semiconductor equipment, is producing the latest generation of NAND built in three dimensions.
Toshiba and manufacturing partner Western Digital have begun turning out samples of the thickest version of 3D NAND to enter production. Memory chips from both companies feature 64 layers of memory cells, instead of the 48 layers that defined the previous generation of 3D NAND.
The new thickness was Western Digital and Toshiba’s big announcement going into the Flash Memory Summit, an industry conference for non-volatile memory, starting this week. One of the event’s themes will likely be the industry's ongoing shift toward 3D NAND production, which has been slowed by competitive prices for planar NAND.
The announcement, however, wrinkled under questions about the memory’s cost per bit—one of the measuring sticks for new generations of memory chips. For years, industry analysts predicted that NAND with 64 layers would match the price of planar NAND and catapult the technology into the mainstream.
But Western Digital and Toshiba have both stayed quiet on pricing and declined to share details with Electronic Design.
To construct 3D NAND, chipmakers pile layers of memory cells vertically on a silicon substrate, so that they act like a single device. There are several ways to connect the layers: Intel and Micron link them with the same floating gate transistors used in planar NAND, while Samsung and Toshiba slide insulators in between the layers to control the flow of electrons.
With either approach, the result is memory chips that provide significantly more capacity than planar NAND. That makes them ideal for solid-state drives inside data centers, smartphones, and personal computers, as well as applications for the Internet of Things.
Western Digital’s memory is called BiCS3, since each memory cell stores up to three bits. Its first incarnation has 256 gigabit — or 32 gigabyte — capacity, but will eventually hold up to half a terabyte on a single chip, the company said. This is combined with “advances in high-aspect ratio semiconductor processing to deliver higher capacity, superior performance, and reliability,” said Siva Sivaram, Western Digital’s executive vice president of memory technology, in a statement.
BiCS3 was an outgrowth of an earlier collaboration between Toshiba and SanDisk, which helped build the New Fab 2 manufacturing plant in Yokkaichi. Western Digital continued the relationship after it acquired SanDisk last year in a $19 billion deal and officially opened the new facility with Toshiba in July.
Western Digital’s bet on SanDisk was a significant departure from its main business of selling hard disk drives, which are only slightly cheaper than planar NAND with the same capacity. The company fell into a memory industry increasingly strained by volatile prices, which shift with the tides of supply and demand. In recent years, the low cost of planar NAND has stifled the market for 3D NAND, causing big chipmakers like Micron to cut jobs while the market turns around.
Despite the fact that NAND prices continue to fall, it has become increasingly difficult to make smaller and more advanced planar NAND devices. Western Digital and Toshiba, along with competitors like Micron and Samsung, are betting the higher capacity of 3D NAND offers a route around that obstacle.
A spokesperson for Western Digital declined to comment on the price of BiCS3, which will enter mass production toward the end of 2016. She said that the company’s long-term plan was “to maintain the cost scaling that SanDisk pioneered in the 2D NAND era,” adding that its new technology will be “very cost-competitive.”
Also being built in the new Yokkaichi manufacturing plant is the latest version of Toshiba’s BiCS flash memory, which has been upgraded to 64 layers. Like Western Digital’s version, the new architecture can hold three bits per memory cell and achieve a 256-gigabit capacity.
The latest version of BiCS — which stands for “bits cost scalable” — was built using Toshiba’s new stacking process, which provides around 40% higher capacity than previous 48-layer processes. Toshiba said that the new stacking process “reduces the cost per bit, and increases the manufacturability of memory capacity per one silicon wafer.”
The new BiCS flash is already sampling, with mass production out of the Yokkaichi facility scheduled for early 2017. At the Flash Memory Summit, Toshiba announced its first products built on the new memory: One example is the BG series of M.2 solid-state drives, which measure only 30mm long and have 128, 256, and 512 gigabit capacities.
Toshiba also declined to share price information with Electronic Design, and did not reveal the price for its new BG solid state drives.
“Planar NAND has hit the wall in terms of significant scalability, which is where 3D BiCS enables an industry cost-down path for higher-density NAND,” the company said in an e-mail statement, but did not provide any timeline for when that might happen.
