There has been a lot of neat new digital technology this year, such as Xilinx’s multislice 2.5D FPGA and Intel’s 3D transistor technology. Yet it will be a while before these impressive developments have a major impact on the industry as a whole, since they target the high end.
Two other advances will have a more immediate impact. First there’s Microchip’s Configurable Logic Cell (CLC), which can be found in the company’s PIC10F32X microcontroller. Second, Adapteva’s Epiphany is a low-power, 16-core accelerator. Both deliver high performance efficiently.
CPLD Plus Micro
The PIC10F32X’s (find Microchip PIC10F32 on sourceesb.com) new features include the CLC (Fig. 1), which is essentially a complex programmable logic device (CPLD). The logic blocks are simpler than a typical CPLD, and there are fewer of them. This also means the CLC takes up less space and uses less power. It is not designed to implement sophisticated logic, but it provides enough support to handle many basic timing and synchronization chores.
There are more sophisticated programmable platforms available. FPGAs are at the extreme end, with more showing up with hard-core microcontrollers every year. In between is Cypress Semiconductor’s PSoC. Its configurable peripheral fabric is more sophisticated but less complex than an FPGA. Still, the idea is the same: provide a configurable single-chip solution. This solution fits into a six-pin, 2- by 3-mm DFN package.
Expandable, Low-Power Multicore
Adapteva’s 65-nm E16G301 Anemone Epiphany has 16 nodes that are only 0.5 mm2 (Fig. 2). This means the multicore chip fits into the same space as a single Arm Cortex core. The nodes are connected in a rectangular matrix that provides communication between nodes. The chip only uses 2 W and comes in a 15- by 15-mm, 324-ball ball-grid array (BGA) package.
The nodes are 32-bit RISC processors with floating-point support. Each core has 32 kbytes of memory. Using the interconnect fabric, a core can access the memory in any other core. There is no cache in the core providing a deterministic environment. Each core has two DMA channels for moving data including to and from peripheral interfaces that are part of the fabric.
The fabric comprises 13 different networks that operate in parallel. The rMesh handles all read operations. The xMesh handles write operations for off-chip communication. The cMesh handles on-chip writes. A reads request initiates a write from the source. Writes operations are asynchronous. Instructions can be synchronized with transfers. The fabrics implement a fixed routing system based on the destination of the data. Total on-chip bandwidth is 32 Gbytes/s/core.
Off-chip communication is performed using four high-speed, 8-bit double-data rate (DDR) links designed to work with FPGAs. The links can be used to connect multiple chips together. The roadmap has chips with up to 4096 cores.
Small is relative. However, designers always appreciate performance and efficiency.