NXP is delivering a unique ARM-based Cortex-M3 microcontroller that can run off serial QPI flash memory as just one of its features. The 90nm LPC1800 product line (Fig. 1) comes in a variety of forms including flash-based versions with up to 512 Kbytes of on-chip flash. This memory is 128 bits wide support full speed, 150 MHz operation.
The on-chip flash supports dual bank operation and simultaneous read and write. This allows real time updates of 512 byte pages. It is based on NXP’s 2T flash cell architecture that provides reliable FN-FN programming as well as true EEPROM operation. There is also a 32 Kbyte boot ROM with on-chip device drivers. The chip has AES decryption hardware including two 128-bit secure OTP memories for key storage. Versions with AES encryption are available on request.
The LPC1800 supports access to quad SPI devices. This interface uses four data lines providing up to four times the performance of normal 1-bit, serial SPI flash (Fig. 2). The micro can also execute code directly from the SPI flash albeit at 40 Mbyte/s transfer rates. This is slower than conventional flash but allows execution using compact, off-chip memory. Quad SPI flash memory is availabe from a range of third party sources in capacities from 512 Kbytes to 16 Mbytes. There is also a RAM-only version of the LPC1800 with additional SRAM on-chip.
The LPC1800 has a range of peripherals (Fig. 3). Communication peripherals on the LPC1800 include two HS (high-speed) USB controllers, an on-chip HS USB PHY, a 10/100 Ethernet controller with hardware enabled TCP/IP checksum calculation, a CAN interface, 4 UARTs, 2 fast-mode I2C interfaces, an I2S interface and 2 SSP/SPI interfaces. There are also up to 80 general purpose I/O pins.
The chip also has an 8-channel DMA controller, two 10-bit ADCs, a 10-bit DAC with data conversion rate of 400k samples/s, 4 timers, and a motor control PWM with quadrature encoder interface. Additional peripherals include a windowed watchdog timer, an alarm timer, and an ultra-low power RTC with 256 bytes of battery powered backup memory. Versions are available with a a high-resolution color LCD controller. Additional off-chip storage is accessible via a smart card interface.
The timer subsystem also includes a pair of 16-bit timers and a state machine. The state machine can handle up to 8 inputs and can drive up to 16 outputs. The system can be programmed for multiphase wave form generation. It can also be used to handle complex serial communication timing for multiple channels.
The LCD, USB, and Ethernet interfaces are optional. The LPC1800 comes in 144-pin and 208-pin LQFP packages plus 100-pin, 180- pin and 256-pin BGA packages. The LPC1800 has up to 136 Kbytes of SRAM with on-chip flash. Flashless LPC18x0 parts have up to 200 Kbytes on-chip SRAM.