Use The MDIO Bus To Interrogate Complex Devices
Semiconductor devices can modify their behaviors based on the parameters written to the internal registers, or the control-voltage levels provided to the input pins. Pin count is sometimes a limiting factor, though, and many designers prefer to utilize the register approach. There are several ways to write the parameters in registers. Some of the most common methods include:
- The control register located at the dedicated address inside the device. This is common among memory devices, such as flash memory. To write the parameters, the host addresses the specific location and supplies the parameter value to this register.
- The chip select specific to the control registers. This type of device provides a dedicated line that, when asserted, accesses the read/write operation to the control registers.
- A dedicated bus to write to the control registers. Dedicated pins are assigned, which a host uses to write the parameters to the device.
In Chapter 22, the MDIO interface is defined in relationship to the accessing and modification of various registers within physical-layer (PHY) devices, and how they relate to connecting to media access controllers (MACs) in 1- and 10-Gbit/s Ethernet solutions. See Figure 1 for an example of the interface.
One MDIO interface can access up to 32 registers, in 32 different devices. A device driving an MDIO bus is called a station management entity (STA), and the device being managed by the STA is called the MDIO Manageable Device (MMD). The STA drives the MDC line. It initiates a command using an MDIO frame and provides the target register address. During a write command, the STA also provides the data. In the case of a read command, the MMD takes over the bus and supplies the STA with the data. Figure 2a illustrates the MDIO frame format, while Figure 2 defines the terminology. Figure 3 shows both the read and write frames.
Chapter 45 specifies the extension to the MDIO, where the following changes are made:
- Capability added to address more registers--up to 65,536 registers in each device.
- More OP-code and ST-code added, which specify the extension (two additional OP-codes and ST-code from 01 to 00).
- Modification of electrical interfaces from the original specification. The earlier specification stated 5- and 3.3-V signal levels. The extension includes signal levels to 1.5 V
The extension specification also allows one STA to drive 32 ports of 32 devices. To access the registers, the STA issues a read or write command to the given addressed MMD and register in that MMD. Where a register isn't implemented, a write command to the unimplemented register or bits doesn't affect the MMD's operation. A read command to the unimplemented bit or register returns a value of 0.
The PHY specification: MDIO/MDC pins are implemented using 5- or 3.3-V TTL signals. For the extension, "0- to 1.5-V" signal logic is specified.MDIO is a bidirectional signal sourced by the host (STA), or by the slave (MMD). The standard specifies timing distinction, such that when the STA sources the MDIO signal, it provides a minimum of 10-ns setup and hold time with respect to the MDC signal. If the MMD is supplying the MDIO signal, the specification allows the clock-to-data delay to be a minimum of 0 ns and a maximum of 300 ns. This is an important factor in the ease of implementing the interface. However, it puts a restriction on the bus bandwidth.
MDIO extended frame format: The master communicates with the slave via MDIO frames. The specification provides for four types of frames.To read or write a register in a specific MMD on a given port, the master (STA) opens the register by issuing an address frame with the port.device.register address. The selected MMD latches onto the address, and then the STA issues a read, write, or read-address-increment frame.
For the write operation, the STA provides the valid data in the frame. For read operations, the STA three-states the MDIO line, and the MMD sources the data. For the read-address-increment, the MMD supplies the data as in Figure 4a, yet increments its address register and will be ready for the next read or read-address-increment command. If the address register contains 0FFFFh, it won't roll over to 0. The frame formats of the various frames are shown in Figures 4a to 4e, and the terminology is described in Figure 4f.
An MDIO example: Vitesse's VSC7226 is a good example of an MDIO interface because it uses a clean method to access more than 32-by-32 registers. This is accomplished via a banking register. The device supports four identical bidirectional channels. Dedicated pins can configure these channels, or individual channels can be configured via the MDIO configuration port.Implementing an MDIO with a general-purpose controller: An MDIO STA is commonly seen implemented in the host CPU, such as a PowerPC or an FPGA. If the ASIC is doing the "housekeeping" and needs to interrogate the board status, the MDIO MMD may be implemented in a general-purpose microcontroller. The STA can be implemented in just about any microcontroller. But the MMD needs a controller that's fast enough to respond in 300 ns. For convenience, we describe the implementation in Ubicom's SX52/IP2K flash microcontrollers because later on, the article discusses the possibility of interfacing to the TCP/IP stack, and remotely interrogating the system over the Internet.Implementing the MDIO STA:> This is easier as there's full control over the clock. The pseudo code in Listing 1 describes the process.Implementing the MDIO MMD: This is a bit more difficult because the device must respond to the clock from the STA. Typically, the clock line would drive the microcontroller's hardware-interrupt pin. When a transition is detected, the MDIO state machine would begin. The implementation is very platform specific. Listing 2 shows a partial pseudo C code.
Internet connectivity to the MDIO STA: One in-teresting possibility is to incorporate the TCP/IP stack provided by Ubicom, and route the data through to the MDIO module. The limitation of this solution is that a designer can only implement the STA, as using an external interrupt complicates this method.
In the solution shown in Figure 5, the MDIO and TCP/IP stack are implemented in a single-chip microcontroller. A user with proper access rights can interrogate the MMDs in a switch, or a router over the Web.
So, the MDIO is a simple yet very efficient bus. The information contained in this article should prepare designers to implement the MDIO bus in a low-cost microcontroller. With the advent of the Internet, interfacing the MDIO to the TCP/IP stack yields a very effective and practical way to interrogate a remote device. The best part is that this solution doesn't add much cost to the managed device.