Extreme ultraviolet (EUV) lithography equipment built by the Netherlands-based ASML. Intel and other chipmakers are betting on EUV lithography to create the next generation of computer processors. Others are turning toward 3D chips for better performance. (Image courtesy of ASML).
The art of shrinking transistors onto computer processors has become vastly more complex over the last several years. Intel, the world’s largest semiconductor company, has struggled to develop the next generation of computer processors on the same two-year schedule it has followed for decades. To complicate matters, processors have stopped getting cheaper with each generation.
An army of researchers, toiling in the shadows of the electronics industry, has been searching for ways around that dilemma. Notably, the French microelectronics laboratory LETI is building mobile processors in three dimensions rather than simply etching transistors onto a flat substrate. It recently extended its relationship with Qualcomm, whose Snapdragon processors are widely used in smartphones and other mobile devices.
LETI has developed a new process for stacking thin layers of semiconductor material, which contain transistors, without degrading the performance of the transistors or the metal interconnects between the different layers. These monolithic 3D chips behave like a single device, generating less heat and consuming less power than traditional chips.
"Instead of having 2D chips, we can replace them with 3D chips that are the same size,” Olivier Faynot, microelectronics section manager at LETI, said in a phone interview. Known as CoolCube, the process is unique in that it weaves together the semiconductor material on the same wafer, as opposed to stitching together existing chips with special nanowires.
That process of stitching together separate wafers is achieved with through-silicon vias (TSV), a rival technology to CoolCube. These nanowires, which are vying to become the next major advance in semiconductors, act almost like rivets holding together steel beams. One of major drawbacks to through-silicon vias, however, is the extreme difficulty of aligning the billions of transistors on each chip precisely, which hurts performance.
As early as two years ago, Qualcomm said that pressure to increase switching speeds and lower costs was forcing it to examine new chip architectures. The company noted that 3D chips would form the basis for future generations of its mobile processors, which it supplies in bulk to smartphone companies. But it was only around a year ago that Qualcomm, which had previously endorsed through-silicon vias, said it would adopt monolithic 3D chips and work more closely with LETI.
The CoolCube method involves two steps. First, a traditional complementary metal oxide semiconductor (CMOS) process, usually at temperatures in excess of 600°C, creates the base layer. Second—and where CoolCube takes its name—a low-temperature CMOS process makes the inner layers of transistors, which are linked to other layers with tungsten interconnects.
According to Faynot, the turning point for the technique, which has been in development for almost nine years, was the discovery of the low-temperature process. The lower temperature ensures that the other layers are not damaged in the lithography process. The CoolCube process also makes aligning the transistors vastly more precise, allowing billions of connections to exist between the layers.
Faynot said the process makes it possible to combine older technology nodes to achieve faster switching speeds and lower power levels. With CoolCube, linking two 28-nm nodes results in chips with performance similar to the 14-nm node. Layering two 14-nm nodes creates a new design that resembles the 10-nm node. Presumably, that progression would continue into even smaller technology nodes.
The semiconductor industry expects to reach the 10 nm node in the next few years, but it will likely have an extremely complex design. In the last five years, the industry has been forced to make semiconductor somersaults to reach the next generation of processors. These include finFET transistors with multiple logic gates and multi-step patterning to deal with the high electrical resistance of smaller chips.
CoolCube, however, has to contend with its own stumbling blocks. Faynot acknowledged that researchers still have to decide which parts of the monolithic 3D chips should carry out CPU functions: Is it a single layer of transistors, or should it be spread out over the entire chip? Another concern, he said, is determining how to test the inner layers of the chip.
Faynot is noncommittal about when CoolCube might be used in mobile devices, though he speculates it will be at least five more years. By then, concerns about the cost and complexity of future nodes could bolster support for monolithic 3D chips. Helping to further that process is the fact that CoolCube does not require new equipment to make. Instead, foundries would have only to adapt current equipment to operate at lower temperatures.
In the meantime, the partnership with Qualcomm is aimed at taking the laboratory designs into fabrication. “Together, we aim to build a complete ecosystem with foundries, equipment suppliers, and EDA and design houses to assemble all the pieces of the puzzle and move the technology into the product-qualification phase,” said LETI chief executive Marie Semeria in a statement.
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