Freescale has finally taken off the wrapping around the 12-core, 24-thread T4240 QorIQ processor (Fig. 1) and the 8-core, 16-thread T4160 AMP (advanced multiprocessing) chips. Earlier coverage highlighted the reintroduction of Altivec (see Altivec Amps Up Latest QorIQ Multicore Chips) but was a little sketchy on the rest of the chip's details. Now we can talk about the those details of these 1.8 GHz, 28nm Power Architecture chips and a bit more about the multicore processing system as well.
|10 Gbit/s SERDES||32||24|
|10 Gbit Ethernet MACs||4||2|
|Power with I/O||30W||25W|
The twelve 64-bit e6500 cores with 128-bit Altivec support in the T4240 are divided into four core clusters. Each cluster has a 16-way, shared 2 Mbyte L2 cache. The clusters are linked to peripherals using a 256-bit wide CoreNet fabric that supports a 40-bit physical address. The cores provide hypervisor, virtual CPU, virtual CPU MMU, and IO MMU support allowing fine grain system partitioning.
The system actually has a 3-tier cache hierarchy with a shared L3 platform cache. The 512 Kbyte L3 CoreNet caches are matched to a 64-bit DDR3 memory controller. From a core perspective, the L3 cache actually consists of the CoreNet caches plus the other L2 cluster caches. There is a data prefetch engine as part of the system mix as well.
The low speed peripherals include things like I2C, UARTs, SPI and USB 2.0. There is also a security monitor.
There are a pair of 16-lane, 10 GHz SERDES. One set handles peripheral interfaces like quad PCI Express Gen 3 with SR-IOV (single root-I/O virtualization), SATA and Serial RapidIO. The other set of SERDES is for network interfaces like Ethernet and Interlaken. These peripherals also have access to hardware accelerators including:
- Frame manager (FMAN) - 50 Gbit/s aggregate; parse, classification and distribution
- Buffer manager (BMAN) - 64 buffer pools
- Queue manager (QMAN) - up to 224 queues
- Radid IO manager (RMAN) - seamless sRIO to DPAA (Data Path Acceleration Architecture) mapping
- Security (SEC) - 40 Gbit/s aggregate IPsec and SSL, public key 25 K/s 1024-bit RSA
- Pattern matching (PME) - 10 Gbit/s aggregate
- Data compression (DCE) - 20 Gbit/s aggregate
- Data center bridge (DCB) - QoS for FCoE, priority flow control, enhanced transmission selection
Multiple chips (Fig. 2) can be linked via Serial RapidIO. Peripherals can also be shared via PCI Express.
The large number of cores, peripherals and hardware accelerators are designed to be as power efficient as possible but additional power management features can have a significant impact on performance and power utilization. Freescale has delivered a range of power management tools. Some work at different levels from individual cores to the entire chip.
|Power Management Feature|
Dynamic clock gating is common these days along with the usual sleep modes. Freescale's drowsy modes retain system state unlike some sleep modes on other micros where the system needs to restart. Cores can automatically put the Altivec engine in drowsy mode when it is not in use.
The cascading power management feature (Fig. 3) operates at the chip level. It is essentially a hardware task scheduler that distributes tasks to cores based on capacity. Unused cores are put in drowsy mode reducing overall power requirements.
Freescale's QorIQ chips target a range of applications from communication to datacenters. They are also useful in the aerospace and military environments.
The QorIQ platform has a rich ecosystem with hardware vendors such as Emerson Network Power, RadiSys, Advantech and Mercury Computers. The software ecosystem includes vendors such as Wind River, Mentor, Enea, 6WIND, and Green Hills Software. Freescale also provides its Code Warrior development suite. Linux with KVM support is avilable as is lxc Linux Container support. The latter is a user space control package for Linux Containers.