Accellera Okays VHDL 4.0

Based on feedback from trial implementations of VHDL 3.0, Accellera has approved VHDL 4.0, which addresses more than 90 issues discovered during the trial period for version 3.0. Accellera, the industry organization focused on EDA standards, plans to release VHDL 4.0 to the IEEE for balloting in 2008 and to support the IEEE 1076-2008 balloting process. The updated standard covers enhancements to major new areas introduced by VHDL 3.0 including generic types, intellectual property protection, Property Specification Language (PSL) integration, VHPI (VHDL Application Programming Interface) integration, and the introduction of fixed and floating-point types. “Accellera’s efforts to enhance VHDL are continuing,” Lance Thompson, Accellera’s VHDL Technical Subcommittee chairman, said in a statement. “Over the past 18 months, Aldec, Cadence Design Systems, and Mentor Graphics have created trial implementations, which have helped us clarify the documentation in the areas that were introduced in VHDL 3.0. In addition, we’ve also incorporated issues resolved by the VASG’s Issues Screening and Analysis Committee.” The VASG is the IEEE’s VHDL Analysis and Standardization Group.