Well, 2012 has come to a close. It looks like all the Mayan “end is nigh” forecasts were good movie hype, but we’re all still here. In fact, fabless companies, foundries, and EDA suppliers have made real progress in preparing for future technology nodes. It’s time to reflect on the past year and what the world has in store for the future in 2013.

From 28 To 20 nm

A year ago, 28-nm capacity was a serious challenge as major fabless companies struggled to get the wafer capacity wanted for their products. As a result of this capacity shortfall, many leading fabless companies pursued one or more backup foundries to ensure sufficient output to meet demand. The shortfall was a function of both insufficient manufacturing capacity and lower than desired yields. Almost a year later, most of the major foundries have aggressively added more capacity to meet consumer demand and simultaneously improved the yield for 28 nm.

2012 was also big for 20-nm process development. Over the last year, the major foundry ecosystems moved from alpha or beta (v0.x) versions of their design rule decks and process design kits (PDKs) to versions more suitable for production (e.g., v1.x). During 2012, many companies took their first steps with 20 nm. My quick count had about half of IC Insight’s Top-20 companies working on 20 nm. The year was dominated by test chips, as we all learned about the new challenges of the 20-nm process, double patterning (DP), new cell-based fill techniques, and other design methodologies needed to make for a successful process.

The big focus in 2013 will be the first production tape-outs for 20 nm. The companies that produced test chips in 2012 are now aggressively moving forward to their first production designs. A lot of learning is behind us with all the work completed in 2012, but there are still some challenges and choices to be made with the industry’s transition to 20-nm production.

Implementation And Physical Verification

As with any new node, yield learning will drive changes to your foundry’s design rule checking (DRC) and double patterning (DP) sign-off decks. Using decks developed by the foundry on the tools they use in-house will ensure the most accurate results and timely updates. Also, allow time in your tape-out schedule to incorporate deck runtime optimizations from your foundry or EDA supplier. These companies have worked very hard to implement as many performance optimizations ahead of time as possible. But with the enormous data volumes of 20-nm designs, there will be some design-dependent surprises. One might ask why these issues can’t all be addressed in advance.

The challenge is that neither the foundries nor the EDA companies have access to the next-node designs ahead of time. With the ever-changing design approaches at each new node, there are unforeseen interactions between the designs, the foundry decks, and the EDA tools. Upfront planning now with the foundry and your key EDA partners will avoid a very painful (and visible to management) fire drill later.

Circuit Verification

With all the hard work over the last year, 20 nm has now solidified for layout versus schematic (LVS) and parasitic extraction (PEX). 20 nm introduces DP and its associated mask 1-to-mask-2 overlay error, which in turn impacts circuit parasitics. Consequently, with 20-nm PEX, you will need to do your analysis for more corners. You will need to decide if you should use all the corners that foundries provide (as many as 15 in some cases), try to do the same number you did for 28 nm, or plan something in between.

Regardless of how aggressive your analysis is, you will have to implement new corner processing methodologies to meet both accuracy and runtime targets. Running each corner sequentially is madness (in terms of cycle time), and throwing them all on multiple machines will chew up a lot of computing hardware and/or EDA licenses. New intelligent extraction tools can process many corners concurrently with only a small impact on runtime versus a single corner. Good options exist if you’re on the lookout for them.

Design For Manufacturability

The move to 20 nm has driven the requirements for dummy fill well beyond the traditional polygon-based approach to a more sophisticated and flexible technology. The emphasis has changed from minimizing fill to maximizing fill to reduce design-dependent manufacturing variability. The benefits of the move to cell-based “smart fill” techniques include reduced file size (versus polygonal-based fill), better symmetry, the ability to fill FinFET layers for 14 nm and below, and easier integration of fill back to the design flow for timing closure.

Throughout 2012, we also saw initial releases of lithography simulation decks to identify lithography hotspots at 20 nm. Simulation is now mandatory for sign-off—no longer a “nice to have.” The challenge now is that lithography simulation must also deal with double patterning for the layers that are affected. Early versions of 20-nm decks perform a complete lithography simulation with double patterning.

The “Next” Node Starts

For years, the industry has used the ITRS roadmap numbering scheme (i.e., 180 nm, 130 nm, 90 nm, etc.) as a convenient means of communicating what the next process node would be. Things started becoming confusing with 90% node shrinks—45 nm became 40 nm, and 32 nm became 28 nm. Well, it has really come off the rails trying to understand what the “next node” is following 20 nm.

What do variants such as N16, 14XM, or 14LPE mean from a design perspective? Setting aside the marketing spin, the next node looks roughly the same from all the foundries—FinFET transistors with a 20-nm process for back end-of-line (BEOL) that uses DP for critical wiring layers.

The introduction of FinFETs will bring new types of design rule checks, but so far, the foundries’ primary DRC supplier already can satisfy them. The foundries are also working with EDA tools such as Calibre to automatically generate the 3D transistor fins so designers won’t have to physically draw them.

To maintain the same use model as previous nodes, designers will only need to draw the gate and the active area polygons. Downstream tools will have automatic modeling of how those drawn rectangles translate to 2D and 3D representations of the actual fins. Verification and parameter extraction then can be accurately performed on these internal models.

One of the biggest impacts of FinFETs will be the need for innovation in device and parasitic models to deliver the required accuracy in physical extraction to drive performance simulations of these new 3D transistors. The nature of the fin geometries will radically change the resistance and capacitance behavior of both the device and the parasitics around the device.

Additionally, from a reliability standpoint, smaller nodes require even thinner oxides under poly, which means electrical overstress (EOS) is a greater concern. Simulation, design methodology, and design reviews can only catch so much. A comprehensive solution for analyzing every transistor and the voltage potential(s) it is connected to is required to ensure that circuits are robust against electrical failure.

For 20 nm, the preparations completed during 2012 will hopefully make the transition from test chips to production as smooth as possible in 2013. At the same time, initial foundry sign-off rule decks created using the foundry reference DRC tools have just been released for the “next node” following 20 nm (whatever we end up calling it: N16, 14XM, or 14LPE). Leading foundries will be continuing their process development, and fabless and IP development companies will also begin their early test chips for this next process in 2013. The industry will take its first steps to adopt FinFET devices, and the transition is guaranteed to bring all sorts of interesting innovation. It should be fun!