# Design Custom Chips That Maximize Battery Life

I’ve always thought it would be great to take a three-week camping trip with my kids. We’d load up our packs and head into the backcountry with our fishing rods and tents, ready for some quality bonding time. My kids, though, are attached to their technology and wouldn’t want to leave it behind. To be honest, I’d hate to go three weeks without listening to music, transferring photos, reading, or even finding directions too.

This got me thinking about developing a tablet computer that could go on our three-week trip without needing a recharge—and specifically about the role that analog/mixed-signal intellectual property (IP) can play in reducing power consumption. The right use of audio codecs, data converters, USB, LPDDR3, HDMI, and MIPI IP can help reduce power consumption in mobile devices.

### Theory Into Practice

Power can be reduced in the digital section, in the analog section, and at the system level. These areas aren’t mutually exclusive. In fact, many applications target them at the same time to save power. Digital power reduction techniques focus on the use of multiple clock and power domains, dynamic voltage and frequency scaling, and power gating. These methods are well reported already, so they won’t be the focus of this article.

The transmitter architecture selection is key, as transmitters often are the dominant source of active power consumption. For example, a USB 2.0 physical layer (PHY) design has two potential driver architectures to choose from: current mode or voltage mode. The voltage-mode driver can minimize power consumption since it draws 50% less current from the supply than a conventional current-mode driver.

A classic USB 2.0 driver requires nominal amplitude of 400 mV for high-speed data transmission into a 45-Ω load (Figures 1 and 2). The static power dissipation from the supply for a current-mode driver is approximately 60 mW. However, the power dissipation from the supply for a voltage-mode driver is only ~30 mW—a 50% reduction.

1. The current-mode driver consumes 58.7 mW.

2. The voltage-mode driver only consumes 29.3 mW.

Voltage-mode drivers can reduce power in a variety of systems. Even in ac-coupled systems such as PCI Express, SATA, or XAUI, a voltage-mode driver draws only 25% of the supply current of a current-mode implementation.

Additional analog power reduction techniques simplify the complexity of the circuit design because folded designs can exploit the complementary properties of NMOS/PMOS devices. Using adaptive biasing and low-power process technologies (e.g., 40-nm LP or 28-nm) decreases transistor dimensions and lowers the supply voltage, reducing overall power consumption.

Let’s apply the analog techniques to an op amp. Analog power reduction techniques require you to plan ahead—like remembering to bring the iodine tablets on a camping trip. When designing an op amp, you need to choose an architecture with only a single (differential) stage, which will help reduce the current consumption.

Maximizing gain while preserving bandwidth and slew rate is now required—or, in layman terms, you have to have enough gain without slowing the system down. Clearly, the op amp needs to be designed to provide sufficient drive while consuming as little power as possible. But how?

First, optimize the bias circuit by reducing the internal stage currents and programming an external current. However, speed, voltage noise, and junction leakage then become issues, as the bias circuit affects them. To get around this problem, reduce quiescent power dissipation by replacing the Class A op amps with Class AB and dynamic op amps. The Class AB output stage is designed to be biased at small currents, so quiescent power dissipation is correspondingly lower.

The basic two-stage differential op amp can be designed in the sub-threshold current region to minimize the current consumption. Keep in mind that this is really for expert designers, as it relies on transistor properties that aren’t used in normal operation. You can gain lots of benefits here, but you risk building an unstable or inoperable circuit.

Analog power reduction techniques also can be applied to a USB 2.0 PHY (Fig. 3). To leverage device characteristics as much as possible to reduce power, level shift down into the low-voltage core device domain as early as possible in the signal path. Most high-frequency analog signal processing then can be done in the low-voltage domain, and in the USB, high-speed squelch detection and the high-speed receive function are implemented using low-voltage core devices.

3. Designers can reduce power in a USB 2.0 PHY by level-shifting down into the low-voltage domain early in the signal path. Then, the high-frequency analog signal processing is performed in the low-voltage domain (green area) rather in the higher-voltage blue area.

The third area where power can be reduced is at the system level. Mobile devices and tablets can waste a lot of power in sleep mode, so building the three-week, no-charge tablet for my camping trip will require an optimized sleep mode.

This can be achieved by employing a collapsible analog supply and collapsible digital supply, as well as low-power versions of the USB standard for mobile applications: link power management (LPM), high-speed inter-chip USB (HSIC), or its successor, super-speed inter-chip (SSIC). The SSIC protocol leverages a USB 3.0 digital transaction layer with the MIPI-based MPHY.

LPM defines a new power sleep state between enable and suspend, so it conserves more power than the present suspend/resume mode. In addition, the sleep mode occurs more often and more quickly, reducing the transitional power states by three orders of magnitude. This slashes the power consumption of USB devices and hosts, and it potentially extends a portable device’s battery life by at least 20%.

HSIC is USB without the cable or the connector. It allows low-power high-speed data transfers (480 Mbits/s) using a source synchronous clocked serial interface. Low power is achieved with 1.2-V LVCMOS signaling levels—that is, there’s no 3.3-V signaling. New specifications for PCI Express manage the wake and sleep modes (including the clocking circuits) to further optimize power at the system level.

### Let’s Go Camping!

Focusing on these three areas where power can be reduced—the digital section, the analog section, and the system level—can help reduce power consumption in mobile devices. I look forward to our three-week backcountry trip, where we’ll take our new tablet computers without worrying about finding an outlet for charging.

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