To improve efficiency in high-power applications, voltage regulators can be used in parallel to double output current capability—if a means of forcing current sharing is provided.

One circuit approach uses sense resistors in series with the load and is applicable to regulators of any type. With a slight modification, it can be placed ahead of the regulators sensing input current. Another method is most applicable to synchronous switchers since it requires the presence of a low-side sense elements, which can be resistors or FETs.

There are times designers may want to parallel regulators to double current or improve efficiency. These include instances when:

1. One wants to use a linear regulator or IC switcher with integrated power FETs, but its maximum current rating is exceeded.

2. A single IC's temperature rise is greater than can be tolerated for surface mounting.

3. Efficiency improvements are justified by reduced total cost or increased battery life.

4. A high-output current requirement dictates a two-phase design. The benefits of dual-phase switchers for high-current applications are widely known. But many dual-phase IC controllers do not provide a way to easily parallel outputs. This is especially true for voltage-mode controllers.

Figures 1a and 1b show adjustable regulator blocks connected in parallel. The feedback (FB) voltages for Figure 1a are with respect to Gnd, while Figure 1b shows three-terminal devices having FB referenced to VOUT. At this stage of discussion, the regulator blocks can be either linears or switchers.

Most voltage regulators use a high-gain feedback loop to slave VOUT to an internal voltage reference so that an error signal at the feedback pin of only a few millivolts will cause a full-scale change at VOUT. The negative feedback with high gain forces VOUT to be a linear function of VREF and the feedback resistor ratio as defined by:

(For Fig. 1a)

VOUT = VREF(RF2/RF1 + 1), where VREF equals VFB (the voltage at FB)       (1)

(For Fig. 1b)

VOUT = VREF(RF1/RF2 + 1) where VREF equals VOUT ­ VFB       (2)

DC errors are mainly determined by VREF accuracy and tolerance of the feedback resistors. When two like regulators are connected in parallel, a small difference in VREF will cause one regulator to source nearly all of the load current until it reaches the current limit. Then, its VOUT will droop until the second regulator, with slightly lower VREF, begins sourcing the remaining load current. Operation in this manner can be acceptable if dissipation and device temperatures remain low enough to avoid thermal cycling.

As load current and regulator dissipation increase, the regulators must share current, so some circuitry must be added to accomplish this. Figures 2a and 2b include RSHARE resistors in series with each output to supply predictable sharing at maximum load current. RSHARE is chosen so the voltage dropped across it at full load is several times larger than the maximum difference voltage between the regulators. Then:

VOUT = VREG1 ­ (IREG1 × RSHARE) = VREG2 ­ (IREG2 × RSHARE) (3)

Full-load difference current = (VREG1 ­ VREG2)/RSHARE      (4)

By choosing a full load difference current of IOUT × 10%, defining Tolerance = T, and setting the maximum (VREG1 ­ VREG2) ­ value to 2 × T × VREG, we get:

RSHARE = (VREG1 ­ VREG2)/(IOUT × 10%) = 20 × T × VREG/IOUT      (5)

Example 1:

For IOUT = 2 A using two 1-A regulators with a ±3% tolerance and VREG = 5 V, RSHARE = 10 × 0.3 V/2 A = 1.5O. Sharing is good, but the voltage drop at full load is 1.5 V or ­30%, which is too much for most loads.

When paralleling voltage regulators, the primary goals of good regulation and predictable current sharing can be obtained by adding a series resistor to sense current in each channel, plus an op amp to amplify and integrate an error signal. The error signal is used to slave one channel to the other by adjusting the slave's feedback voltage until the voltage across each sense resistor is equal. This method, as depicted in Figures 3a and 3b, is simple and relatively efficient for currents ranging from zero to a few amps. And, it works equally well for synchronous and nonsynchronous switchers and linear regulators.

The grey highlighted circuitry in both figures consists of sense resistors, RS1, RS2, and a differential integrator. For regulators without current-sink capability that must operate at light load, ROS is added to supply a small no-load offset to the integrator. Without ROS, as the load current falls enough to allow the voltage across either RS1 or RS2 to be less than the op-amp offset voltage, the slave VREG2 voltage can rise. RF3 sets the control range of VREG2. The sharing configuration of Figure 3b works with all regulator types, including three-terminal regulators.

Selecting the sense resistor value is a tradeoff between efficiency and the increased cost of specifying a low-offset op amp. Select U1 for low offset voltage and rail-to-rail capabilities. In Figure 3a, the op amp can be an LMV931M5 and powered from VOUT in the range of 1.5 to 5.5 V. Or, it can be a part like the LM7301M5 in the VOUT range of 2.2 to 30 V. Both are available in SOT23-5 packages with VOSIN, provided that VIN ­ VOUT is greater than 1.5 V.

In Figure 3b, U1 is powered from VIN and needs to have an input common-mode range active at the positive rail, as do the LMV931M5, LM7301M5, LMC7101M5, and LMC8101M5. Select ROS to supply a small voltage drop across the integrator input resistor equal to the op-amp offset voltage. Equations 6 and 7 are used to select RS for each regulator based on the lesser of the maximum power one is willing to dissipate at full current in each RS. Or, the maximum voltage drop tolerable across each RS. Equation 8 is used to select the maximum offset voltage allowed for the op amp selected for a permitted IOUT difference current, ID, at full load:

RS = 4 × (Power dissipated in each RS) / IOUT2(6)

RS = 2 × VRS / IOUT, where VRS is the voltage drop across each RS(7)

VOSmax = ID × RS/2      (8)

The minimum value for each RS is based on the accuracy desired for the current match. The maximum value for RS is determined by either its available voltage drop or power dissipation. A desired current difference of 10% or less (ID ¾ IOUTMAX/10) requires a VRS of at least 10 times the offset voltage of U1.

Example 2:

For IOUT = 2 A using two 1-A regulators with a ±3% tolerance and VREG = 5 V, let us choose RS dissipation at 100 mW. Then, RS = 4 × 0.1 W/4 = 0.1 (omega). And, VOSmax = 2/10 × 0.1/2 = 10 mV. For the circuit of Figure 1a, ROS is chosen to supply enough current to drop 10 mV across a 1-kO resistor, or 10µA. So its value is 5 V/10 µA = 500 kO. RF3 must supply a control range large enough to force VREG2 to its full output current range. Choose its value with U1's output at zero and its current greater than (VOUT × 2 × tolerance %)/(RF1 + RF2) resulting in:

RF3 >= VFB(RF1 + RF2)/(2 × VOUT × tolerance%), where VFB is the voltage at FB      (9)

Figure 4 shows a more detailed view of Figure 3a with VREG1 and VREG2 drawn as synchronous switchers. Because synchronous switchers sink and source current, ROS can be omitted and the VOS requirement of the op amp can be relaxed by 50%. Equation 8 then becomes VOSmax = ID × RS.

Example 3:

For IOUT = 10 A using two 5-A regulators with ± 3% tolerance and VREG = 5 V, let us choose RS dissipation at 250 mO. Then, RS = 4 × 0.25 W/100 = 10 mO and VOS max = 10/10 × 0.01 = 10 mV. Losses can be further reduced by a factor of three by choosing a better op amp such as the LMV711M5, which has a 3-mV maximum VOS, reducing the minimum RS values to 3 mO.

At a higher current of 33 A, for example, even 1 mW of series resistance adds 1 W dissipation. Here, series resistors tend to be relatively large and expensive, add significant loss, and produce unwanted temperature rise. By using the RDS(ON) of the low-side FETs as the current-sense resistors, no additional losses need to be introduced. Current-sharing accuracy will vary somewhat due to RDS(ON) mismatch. But it will be within an acceptable range as long as the FETs are mounted on the same heatsink or pc-board copper area.

Measuring small voltage drops across the RDS(ON) of the bottom FETs in the presence of a switching-waveform amplitude that is 100 to 1000 times larger seems difficult at first glance. The circuit in Figure 5 shows one way to do this relatively accurately with inexpensive parts. The measurements do not require absolute accuracy since it is the integrated difference voltage that is used as the error signal.

The grey-tinted current sensing circuit of Figure 5 uses a dual op amp, U1, to measure and amplify (× 10) the small negative voltage present across each lower FET during its conduction period. This sensing method requires a low-side FET, making it applicable to synchronous switchers.

Diodes D1 and D2 in Figure 5 prevent the large signal swing at each switch node from overdriving the op-amp inputs. This allows U1 to be a low-voltage, single-supply dual amplifier. Its most critical specs are low offset voltage and wide bandwidth, since it is measuring signals of

The part selected, an LMV722MM, provides a 10-MHz bandwidth with 3-mV maximum offset. It can be powered from a wide range of sources, often including the regulator output if it falls within the needed 2.2- to 5.5-V supply range. In this example, it is easily powered from the 5-V gate-driver supply.

U2 is used to integrate the difference voltage from the U1 outputs to form an error signal with very high dc gain. Figure 5 shows the error signal summed into the slave-channel feedback node by RF3. RF3 is chosen to be much larger than RF1 and RF2 to make the error signal adjustment range

For a fourth example that explains how the circuit in Figure 5 can combine 30-A, 1.2-V channels into a single 60-A output, see "Double Your Output Current With Parallel Voltage Regulators (Part 2)" at www.elecdesign.com, Drill Deeper 9279 ED Online 9270.