Throughout its history as a leading logic-synthesis tool, the Synopsys Design Compiler has endeavored to stay ahead of the curve as new challenges loomed in IC implementation. In this year’s edition of the company’s flagship product, interconnect delays are the focus of major improvements in the tool.
Two major factors have risen to the top in terms of interconnect delays, says Gal Hasson, senior director of marketing for RTL synthesis, power and test automation at Synopsys. “One is wire lengths and the other is coupling capacitance. At today’s advanced nodes, wires are fabricated taller and with less spacing between them,” says Hasson. “As a result, the effect of coupling capacitance is greater, presenting more of a challenge for correlation and predictability.”
The upshot is that designers are once again, as they did earlier in this decade, experiencing the “ping-pong” effect of doing synthesis runs and performing placement and routing only to find that they could not close timing. This meant returning to synthesis and starting over. The answer to this issue in 2005 was the introduction of topographical technology and better correlation to layout.
Today’s challenges require a different approach, however. According to Hasson, two types of iterations hamper productivity. “The first has to do with floorplan exploration, which creates synthesis iterations. The other is the old problem between synthesis and place and route, where you think you’ll meet your design goals and then can’t achieve closure,” Hasson says.
In Design Compiler 2010, Synopsys believes it has come up with a solution that meets the challenges of physical implementation for today’s systems-on-a-chip (SoCs). According to the company, the tool provides a better starting point for physical implementation, providing predictable design closure and faster placement runtimes.
In terms of providing a better starting point for Synopsys’s IC Compiler, Design Compiler 2010 offers pushbutton floorplan exploration from within the Design Compiler environment. By affording access to the IC Compiler floorplanner, this enables what-if analysis of various floorplan options and permits floorplan issues to be addressed in synthesis.
Design Compiler 2010 also delivers physical guidance to IC Compiler. These combine to shorten place-and-route runtimes (about 1.5 times faster) and also provide tighter correlation (about 5%) between synthesis and place and route.
“We introduced new physical optimizations that have never been done in synthesis,” says Hasson. This includes more accurate modeling of coupling capacitance. “Once we did that, it was clear that we could pass physical guidance to IC Compiler in addition to the netlist.” Some timing-driven placement is now done in Design Compiler, as well as high-fanout optimizations. “As a result, the netlist and guidance handed off to IC Compiler is much better,” says Hasson.
A second important revamp in Design Compiler 2010 is a new infrastructure that supports multicore platforms. Synopsys created an optimized scheme of distributed and multi-threaded parallelization techniques. On average, users can expect runtimes that are twice as fast on a quad-core machine. At the same time, there is no deviation in quality of results.
“We built the infrastructure so it will scale in the future to eight- and 16-core CPUs,” says Hasson. “As these appear, we’ll tune and improve Design Compiler to take advantage of the additional cores.”