Traditional IC test-pattern generation, including stuck-at, transition, small delay, and bridge, produces high-quality tests that detect most defects. All of these tests use fault models that define fault sites at IC gate boundaries.

However, a significant population of defects (perhaps up to 50%) occurs within the gates, or cells. Many cell-internal defects can be detected with traditional test methods, but some require a unique set of stimulus to excite and observe the defect. It is important for applications that require near-zero defects to properly define fault models that target these cell-internal defects.

Table of Contents

  1. Introduction
  2. A Brief IC Test Backgrounder
  3. Basics Of Cell-Aware ATPG
  4. Cell Characterization Process
  5. Determining The Best Test Suite
  6. Summary
  7. References


Introduction
To better define new fault models, we will explain how a cell-aware automatic test pattern generation (ATPG) method characterizes the library cell’s physical design to produce a set of user-defined fault models. Thus, the actual cell-internal physical characteristics and reactions to expected defects are used to define and target faults.

This article demonstrates how some cell-internal defects can escape existing fault models and explains the process of generating these cell-aware, user-defined fault models (UDFMs).

A Brief IC Test Backgrounder
The basic premise of IC test is to deliver specified test patterns to a chip. Subsequently, we detect defects within the chip upon observing its responses to those patterns. We generate test patterns from fault models that represent potential defects with simple properties. We achieve access to internal nodes of the chip through scan chains. The scan structures turn sequential logic into shift registers, which are control-and-observe points that can be loaded and observed from tester equipment.

Fault models in common usage include stuck-at (stuck-at-zero, stuck-at-one), transition, small delay defects, deterministic bridge, and multiple detect. These fault models are based on observations of silicon defect behavior and are developed by the electronic software design automation (EDA) vendors. They are commonly available to anyone using the test pattern generation software.

However, these tests all look for defects only at the boundary of standard cells, or gates, and not the defects that occur within the standard cells.1 TSMC has stated that “for 90 nm and beyond, a significant number of manufacturing defects and systematic yield limiters lie inside library cells.” 2 There is a recently utilized methodology of characterizing library cells to identify potential defect locations inside the cells and specific test patterns that are necessary to detect them.

Multiple studies have shown that tests generated using cell-aware UDFMs will find defects that the normal test methods will miss. One such study by AMD found that after testing 600,000 die, more than 32 die passed the standard manufacturing stuck-at and transition tests, but failed the UDFM tests. 3 This represents a reduction in defects per million (DPM) of defective devices by 55.

Basics Of Cell-Aware ATPG
Before stepping through the process of generating cell-aware patterns, let’s first look closer at why it is necessary. A simple AND gate with two inputs and one output is very simple to understand and model. The logic model has four possible input combinations: 00, 01, 10, and 11. The 11 combination produces a 1 at the output. All other combinations produce a 0.

ATPG tools, though, will only use as many input combinations as necessary to detect all the faults at the logical model. In the case of stuck-at fault models, there is a potential that any input or output is stuck at a 0 or 1. To test for a stuck-at-0 at an input, a 1 is applied to that input with other inputs set to values that enable the input being tested to dictate the value of the output.

In this example, we can detect all stuck-at faults if the 01, 10, and 11 input combinations are used. As far as the logical model is concerned, there is no value in generating a pattern that produces a 00 input.

In the case of this simple AND gate, there isn’t an actual cell-internal defect that would be uniquely detected with a 00 input. Cell-internal defects would be detected by one of the other combinations, so a cell-aware model would not be necessary for this cell.


1. Shown is a XOR-model truth table and corresponding stuck-at coverage.

Now, let’s look at a more complex model. Consider an XOR gate. Traditional stuck-at tests will target a 0 and 1 at every port. A table shows that if the pattern sequence of 00, 01, and 10 is applied to the XOR inputs, then all the stuck-at faults are detected (Fig. 1). There is no reason to apply 11 to the inputs. ATPG for a stuck-at fault model would be fully satisfied.

A look at the layout of the XOR gate, though, reveals multiple potential bridge locations within the cell. A few are only detectable with a 11 input. As shown, a resistive bridge at D33 between VSS and the gate of transistor M3 would appear as a short to 0 at the A input (Fig. 2). 4


2. This depicts the physical layout of the XOR cell with a bridge between M3 and VSS. (Open Cell Library developed by Nangate)

Yet the resistive short is not strong enough that transistor M8, also connected to the A input, is disabled. This is because the resistance of the vertical poly allows for enough voltage across it for transistor M8 to operate.

Through analog simulation, we have seen that this particular resistive bridge can only be detected by applying 11 to the inputs of this XOR gate. Consequently, the stuck-at patterns mentioned above would not detect this cell-internal defect.

During normal ATPG, we produce thousands of patterns. So even if a traditional fault model did not target the defect described above, it could be detected through random chance. But when considering millions of gates in a design, it isn’t effective to rely on chance to detect these potential cell-internal defects at every gate.

One option would be to apply every possible combination of inputs at every gate. We call this fault model a gate-exhaustive fault model. It could be effective in detecting many cell-internal defects because it would apply every possible combination. However, it’s completely impractical to apply such an exhaustive set of patterns.

You might think that a logic model with eight inputs would require 28 (256) gate-exhaustive combinations. This isn’t true because some gates can effectively produce a result at the output from a subset of its inputs.

When a gate is embedded in a real circuit, an input to the gate could be driven to an unknown state (X value) during pattern generation and simulation. A two-state gate-exhaustive pattern would require every gate input to be at a 1 or 0 state.

An effective gate-exhaustive fault model would need to consider a third don’t-care state applied to inputs. Thus, an eight-input logic model could require as many as 38, or 6561 patterns.

You could run simulations of these combinations to find the ones that are necessary and do not produce a value at the output. As a result, you will still have between 28 and 38 combinations for the eight-input model. Many of the gate-exhaustive combinations will not provide unique defect detection and will be wasted ATPG and pattern-application time.

Furthermore, some defects inside cells can manifest themselves as timing-related defects and are not detectable using static tests. An efficient method is necessary to target static and dynamic cell-internal defects for low DPM products. This is the objective of cell-aware ATPG.

Cell-Characterization Process
Cell-aware ATPG starts with an automated characterization process that produces a UDFM file readable by test tools such as Mentor Graphics’ TestKompress and FastScan. Each fabrication process has a set of technology libraries used to describe the logic behavior and physical layout of the lowest-level component in the netlist. Typically, the ATPG and time-based simulation processes are based on a logic library composed of logic models. A corresponding physical library exists for the IC layout.

The cell-aware characterization process starts with an extraction process of the physical library. This will produce a transistor model of each cell and identifies resistive and capacitive properties within the cell models. Extracted resistance within the cell represents conductive paths with the potential for open defects, and extracted capacitance represents possible locations of bridge defects.

Each potential defect is simulated in SPICE against an exhaustive set of stimuli to determine if there are sets of cell inputs that produce an output different from the defect-free result. The set of stimuli for each cell that produces outputs different from the defect-free case is essentially a conversion of the simulated physical defects into a logic-level fault model.

Currently, users can apply their own custom set of input stimulus at cells, instances, or between instances with a UDFM file. We can directly apply the fault models produced in the cell-aware characterization process as a UDFM file for ATPG.


3. The cell-aware characterization process and flow differs from the normal flow in the characterization of the design library to generate a UDFM file as input to ATPG.

Let’s look at the characterization process a little closer, beginning with extraction (Fig. 3). The physical technology library is necessary because the silicon layout of a standard cell can vary from one technology library to another. Our goal is to convert potential physical defects that can manifest themselves in the technology cell layout into UDFM fault models that ATPG can process.

Each technology cell has a layout GDSII that’s read into the automated characterization process for extraction. Each extracted cell results in a transistor-level design with parasitic resistance and capacitance. A resistance location represents a conductive path with the potential for an open defect, and capacitance identifies locations with the potential for a bridge defect.

Each transistor-level design representing the technology cells is then simulated in Spice. We perform a baseline analog simulation with an exhaustive set of input combinations. Next, we add resistive defects and simulate those against the set of stimuli at the extracted resistance or capacitance locations to see if any input combination produces a faulty output. If so, then that input combination would be effective in detecting the defect. Repeat this process for every defect you want to detect.

The simplest case is to simulate each capacitive location with a 1-Ω resistance representing a hard bridge. There are many possibilities to model other defects using analog simulations. For example, various resistances can have different effects and might detect defects that are not detectable with hard shorts (1-Ω bridges). In addition, simulating over multiple cycles is also useful to detect bridges or opens that are observed only as dynamic defects.

The final process in cell-aware characterization is to convert the list of input combinations into a set of the necessary input values for each defect within each cell. Because this information is defined at the cell inputs as logic values, it is basically a logic fault model representation of the analog defect simulation.

This set of stimulus for each cell model is used as a UDFM file for ATPG. Within the UDFM file, a simulated defect (now a fault) can have one or more input combinations. In the example shown, ATPG will try to find any of the three input combinations when targeting this fault (Fig. 4). If any one of the combinations is applied, then the fault is marked as detected and other combinations are not necessary.


4. This example of a UDFM file shows three input combinations each that can detect defect “my_stuck_01.”

Note that because the cell characterization process is performed for all cells within a technology library, any design using that technology can read in the same cell-aware UDFM file. Characterization only needs to occur once and then can be applied to any design on that technology node.

Determining The Best Test Suite
There are two approaches to determining the value of cell-aware ATPG for a particular design. The first technique is possible if a sufficient set of production test escapes exists. These devices passed production test but were later found to be defective.

First, retest the devices with the production test patterns to make sure they did not break down after initial testing. Because field return test does not affect volume production, we can apply a full set of test patterns. Simply apply the set of new test patterns under investigation.

If 100 field returns are tested and 10 fail the new patterns, then that could represent a significant population of defect detection, possibly reducing the escape rate by 10%. The larger the number of field returns available, the better our ability to estimate the potential impact these patterns will have in production.

The other approach is to add a sample of cell-aware and possibly other various pattern types being investigated to the production test suite. You would add these patterns to the production test patterns and perform them after the normal production test passes.

After testing many devices in production, the effectiveness of the new pattern types can be determined based on the amount of unique detection they provide for parts that pass the baseline tests. Then you would adjust the number of patterns for each pattern type based on their ability to uniquely detect defects. We often call this approach adaptive test.

Summary
Some defects inside a standard cell might not be detected using common fault models. The cell-aware ATPG characterization process can create a set of fault models based on the simulated behavior of defects within the cell layout.

As a result, a higher-quality pattern set can be produced. Silicon results have already shown significant additional defect detection beyond standard stuck-at and transition patterns when using cell-aware ATPG.

References

  1. “Defect-Oriented Cell-Aware ATPG and Fault Simulation for Industrial Cell Libraries and Designs,” F. Hapke, et al, ITC 2009
  2. M. Sharma, et al, “Faster Defect Localization in Nanometer Technology based on Defective Cell Diagnosis,” ITC 2007
  3. F. Hapke, et al, “Cell-Aware Analysis for Small-Delay Effects and Production Test Results from Different Fault Models,” ITC 2011
  4. Nangate Open Cell Library License, Version 1.0, February 20, 2008, openlibrary@nangate.com