SPICE Selects SMPS Capacitor

Feb. 1, 2002
Power electronics benefit from SPICE simulation by eliminating a prototype's possible smoke or heavy noise. For example, we can use SPICE to the bulk capacitor in the front-end stage of any power supply.

Power electronics benefit from SPICE simulation by eliminating a prototype's possible smoke or heavy noise. For example, we can use SPICE to the bulk capacitor in the front-end stage of any power supply. Fig. 1 shows a very familiar waveform: the ripple superimposed over the dc rail. With a few algebraic lines, you can quickly derive the diode conduction time:

Where:
Tc=Diode conduction time
Vmin=Valley ripple
Vacin=AC line input
Fline=Mains frequency

Also, the necessary value for the bulk capacitor to fulfill the ripple requirements imposed by your design constraints:

Where:
Cbulk=Bulk capacitor value in μF
Vripple=Ripple voltage
Vpeak=Peak ripple voltage
Pout=Delivered output power

Suppose you want to assess the ripple evolution, and thus the rms current circulating in Cbulk, over the whole input voltage range of your power supply. Fig. 2 offers a solution that emulates the SMPS consumption (70W kept constant by the feedback loop), a B-element source can do the job for you. Using an in-line equation, the following line automatically adjusts the current drawn from the line to keep the product V×I equal to the power parameter:

IsSpice4 B1 out 0 I=70/V(out)
PSpice G1 out 0 value={70/V(out)}

With such a line, whatever the rail voltage out, the load permanently draws 70W and eases the total range sweep. Because of the possible division by zero, you need to place an .IC statement after the capacitor value as exemplified on the picture. A UIC keyword tells the simulator to start with this initial voltage during the bias point calculation and everything should properly converge.

Should you want the simulator to automatically find the capacitor value that offers a given ripple (e.g. 20Vpp), a simple objective function can do the job, providing your simulator features an optimizer. In IsSpice4, authorize the simulator to vary CBulk ±85% from an arbitrary value (say 500 μF to start), and include an objective function to help find the capacitor value that brings it close to zero. It could look like:

setcursor 0 35m
setcursor 1 45m
ofunc=(pk_pk(VOUT)-20)^2
print ofunc

The first two lines instruct the simulator to isolate a 10 ms period between 35 ms and 45 ms. Then, you must define a measurement that will be minimized when you get your answer. This is the ofunc statement that delivers zero when the peak-to-peak ripple reaches 20V. During the simulation, the optimizer will sweep the CBulk value to quickly bring ofunc close to zero. After only a few seconds, you will get “optimized results:” cbulk capacitance=263.123812U.

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About the Author

Christophe Basso

Christophe Basso is a Technical Fellow at ON Semiconductor in Toulouse, France, where he leads an application team dedicated to developing new offline PWM controller specifications. He has originated numerous integrated circuits among which the NCP120X series has set new standards for low standby power converters.

Further to his 2008 book “Switch-Mode Power Supplies: SPICE Simulations and Practical Designs”, published by McGraw-Hill, he released in 2012 a new title with Artech House, “Designing Control Loops for Linear and Switching Power Supplies: a Tutorial Guide”. His new book is dedicated to Fast Analytical Techniques and was recently published by Wiley in the IEEE-press imprint under the title “Linear Circuit Transfer Function: An Introduction to Fast Analytical Techniques”.Christophe has over 20 years of power supply industry experience. He holds 17 patents on power conversion and often publishes papers in conferences and trade magazines including How2Power and PET. Prior to joining ON Semiconductor in 1999, Christophe was an application engineer at Motorola Semiconductor in Toulouse. Before 1997, he worked as a power supply designer at the European Synchrotron Radiation Facility in Grenoble, France, for 10 years. He holds a BSEE equivalent from the Montpellier University (France) and a MSEE from the Institut National Polytechnique of Toulouse (France). He is an IEEE Senior Member.

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