Today’s high-density application-specific integrated circuits (ASICs) are no picnic to test, sometimes nearly impossible. The solution: design for testability (DFT), developing circuit design and test strategies concurrently. Changing the total design and test process can be challenging, but the benefits from DFT can far outweigh the frustrations.
The additional logic needed when incorporating testability into any circuit typically increases the amount of silicon, and sometimes the space required to implement the design. The savings from enhanced testability usually do not show up until the design cycle time and testing costs of the circuit and its end system are analyzed.
Fault simulation is an important part of designing for testability. This technique enables you to evaluate your test patterns to determine whether these patterns detect faults. Faults may occur during either the design-tooling stage or the circuit-fabrication stage.
Adopting DFT principles early in the design process ensures the maximum testability for the minimum effort. These guidelines emphasize that test is a part of the design flow, not a process done at the end of the design cycle. Three basic elements must come together to make a successful ASIC circuit:
o Logic design, including schematic capture, library selection, synthesis and simulation.
o Logic testability, including fault-detection and test-application criteria within predefined cost and time-scale budgets.
o Vendor’s manufacturing capability, including processing and packaging.
The Need for Testability
You are familiar with the trade-offs among gate arrays, standard cells and full custom devices when designing ASICs. You also know the vendor-selection process. But the aspect of test capability and testability is often overlooked.
Testability could be ignored when typical designs were only a few thousand gates. These designs were implemented first and then turned over to a test engineer or a vendor to create a test program for production.
As design complexities increased, this approach to testing became futile. Successful high-density ASIC design and manufacturing demand that circuits be put together with testability incorporated into the design process.
Although testability imposes additional constraints in the design phase, design verification and test can be unmanageable if ignored until the design is completed.
Test-Time Cost
Test cost, as it relates to time, is a simple calculation. Most commercial testers cost between $2 million and $3 million. Under normal circumstances, the tester depreciation, plant, operator and support personnel costs are between 10 and 20 cents per test second.
Brute-force test approaches often generate a large number of test patterns. Since test patterns are run at multiple power supply values and possibly at multiple temperatures, inefficient pattern sets can severely impact the test costs of a complex ASIC.
Time to Market
Surveys indicate that 40% of an ASIC’s development cycle is devoted to test insertion and pattern generation. This figure is expected to increase as device complexity increases.
The intent of a DFT strategy is to achieve high fault-detection test programs in reduced time (Figure 1). The obvious cycle-time reductions result from designed-in testability (the elimination of iterative redesigns resulting from poor design practices), and from automatic test pattern generation (ATPG).
The temptation is to rush to market with devices that are not completely testable or tested. The results are higher-than-desirable manufacturing and field-maintenance costs.
Fault Coverage and Cost of Ownership
Figure 2 shows the economic relationship between time to market and system-manufacturing and field-maintenance costs vs fault coverage. Point 1 represents the case where the target date for the introduction of a product into the market constrains the product’s development time. To meet a shortened development schedule, comprehensive testability development and actual testing are sometimes sacrificed. Higher manufacturing and field-maintenance costs are often the result of such a development strategy.
Point 2 represents the case where DFT and ATPG techniques are employed to develop devices that are completely tested. This situation allows an economic optimum that is more favorable to long-term manufacturing and maintenance costs.
Figure 3 is a plot of the relationship modeled by T.W. Williams for fault coverages of 90% or greater.
The Williams model is:
D = [1-Y(1-T)] x 100
where: D = defect level in percent
Y = theoretical functional process yield
T = fault coverage of the test program used
To explore the Williams model briefly, assume that the ASIC vendor has a silicon and assembly process yield of 70%. If the fault grade of the test program is 90%, the defect level is projected to be 3.5% or 35,000 ppm.
A study of the model shows that the silicon and assembly-process yield becomes an insignificant term when the fault coverage of the test program is very close to 100%.
Theoretical and experimental studies conclude that a high-fault-grade test-pattern set is required for low-defect-level ASIC devices. This type of pattern set is nearly impossible to obtain through brute force. The requirements for a high-fault-grade pattern set are:
o An ATPG tool.
o A fault grader.
o A testable design that meets the constraints of the ATPG tool.
A DFT strategy has performance and area costs. Now the cost of new tools has been added. Benefits such as lower test costs and reduced time to market have been mentioned. These benefits are real, but often hard to quantify. Reduced cost of ownership is another major benefit and is easy to quantify.
The Rule-of-Ten term is commonly used to point out that there is a cost associated with finding a defect in a packaged device before it has entered the assembly process. The cost of finding a defective device after assembly onto a PCB is an order of magnitude more than before assembly.
This continues until the cost to discover a defective device in a system at a customer’s site is three orders of magnitude higher than before assembly onto a PCB. The lowest cost of ownership is to find the defective units before they are shipped from the vendor.
The lowest cost of ownership can be obtained by providing the ASIC vendor with an efficient, high-fault-detection set of test vectors. These DFT methodologies provide lower cost of ownership with the added benefit of reduced time to market.
Developing Testability Strategies
This step-by-step strategy defines a DFT process:
1. Select a technology that provides enough performance and gate-count margin to allow the insertion of testability.
2. Commit to using testability design practices. And review them with the design team before the design begins. Add a testability commitment to the design-requirements document developed for the design project.
3. Establish a fault-grade requirement. This can usually be provided by the manufacturing or quality organization. Establish this requirement before the first design review. Add the fault-grade requirement to the design-requirements document.
4. Decide if IEEE 1149.1 will be a system requirement. When implemented in an ASIC device, IEEE 1149.1 allows test of the interconnect between devices on a PCB through a four-pin test bus.
5. Select an ASIC testability approach based on gate density:
o Designs with fewer than 10k gates are not generally complex enough to require structured test approaches.
o Designs with more than 10k gates but less than 20k gates are candidates for structured techniques.
o Designs with more than 20k gates usually require structured approaches to achieve high fault grades.
6. Choose structured tools. Scan testing is the preferred structured approach for sequential logic.
7. Establish a diagnostic functional-pattern set to expedite debug. This is an important step in decreasing the time to market for an ASIC device.
8. Generate high-fault-grade test patterns to ensure the best possible quality level attainable with that set of patterns.
9. Simulate test patterns and timing to verify both functionality and performance of the device.
Figure 5 contains a flow chart that steps through the DFT process.
Summary
To fully realize the benefits that DFT can bring to high-density ASIC designs, keep these considerations in mind:
o Successful high-density ASIC design and manufacturing demand that testability be incorporated into the design process.
o Adopting DFT principles early in the design process ensures the maximum testability for the minimum effort.
o Savings from enhanced testability will not show up until the cycle time and testing cost of the circuit and its end system are analyzed.
About the Author
Robert Gruebel is a Senior Member of the Technical Staff and Test Development Manager in ASIC Engineering Services at Texas Instruments. Texas Instruments Inc., 8330 LBJ Freeway, M/S 8358, Dallas, TX 75243, (214) 575-2577.
Copyright 1995 Nelson Publishing Inc.
March 1995
|
|