By using design-for-test techniques such as scan insertion, ASIC and IC designers have approached 99.9% fault coverage rates for stuck-at faults. But these types of test are not capable of detecting all manufacturing defects.
Among these unnoticed faults are AC defects, which occur primarily at high clock speeds. And with increasing design density resulting from deep-submicron designs, these AC manufacturing defects are a growing concern.
To ensure that a device can operate at the maximum specified clock rate, the automatic test pattern generation (ATPG) tool must generate tests for the device’s critical paths. Critical-path analysis (CPA) products can analyze devices to identify the critical timing paths, based on device clock and data relationships.
ATPG tools originally designed for stuck-at testing have been extended to include tools that automatically generate critical-path tests. These tests augment the pattern sets provided to detect manufacturing defects. The path tests can discover dynamic failures which occur along the defined paths. Not only do these tests contribute to improved product quality but also provide the capability to get to first-pass, at-speed working silicon.
Dynamic Defects
Dynamic or AC defects affect device timing. These types of defects, which cannot be adequately detected with functional test, are loosely categorized into two groups: gross AC defects which may cause timing failures in any portion of the design, and small AC defects which will most likely affect critical timing paths in the design. Critical-path testing targets the latter, but may pick up some of the gross AC defects if they affect the tested paths.
Process variations or defects may result in the device being functionally correct but defective when operating at speed. The cumulative effect of these process variations along critical timing paths in the design may ultimately result in device failures. Dynamic defects are more difficult to detect because they require an added variable to determine if the tests pass or fail.
Consider the simple critical path shown in Figure 1. The path is defined starting at Q of FF1 (launch point). The critical path proceeds through gates G1, G2 and G3 and ends at D of FF2 (capture point).
If the device is to operate at speed, a signal transition beginning at the launch point must arrive at the capture point within a predetermined time, such as 10.0 ns. The device path actually takes 8.0 ns, nominal. If process variations in the chip result in each gate operating slow by 2.0 ns, the device would fail because the proper value would not have been captured into FF2.
Critical-Path Testing
To detect small AC defects occurring along a critical path, a two-step test is required. Using the circuit in Figure 1, assume that the goal is to create a test capable of detecting the example defect. Then assume that the designer wants to create a test to verify that a low-to-high transition starting at the launch point is able to propagate to the capture point in 10.0 ns.
To create such a test, initialize FF1, the launch point, to a 0. Also, initialize the capture point to a 1. The first part of the test requires that the designer launch the transition. This can be accomplished by clocking C1 with D=1. To capture the transition, clock C2 at time 10.0 ns.
If the path is defective, the capture point would not change. If the path is operating correctly, it should capture a 0. In this case, since the path has an inversion, the capture value to pass the test will be the inverse of the final transition value of 1. Finally, the captured value must be propagated to a primary output.
The test requires two clocks, one for launch and one for capture. Consequently, critical-path tests are often referred to as two-clock tests or sequential tests.
Critical-path testing can become more complicated. The path must be fully sensitized so the transition value does propagate from start to end points. This condition can be difficult to establish, depending on device complexity. When adding tristate logic, buses and memories between the launch and capture point, the test becomes more difficult to establish.
Tools and Techniques
Conventional methods used for critical-path testing include running design functional patterns at speed and creating critical-path tests manually. The first method is limited in coverage because the functional test may not fully test the critical paths. The second method is time-consuming.
High-end design teams are moving to an automated approach which couples CPA tools and ATPG. VLSI devices contain hundreds or thousands of critical paths. CPA tools can automatically determine critical paths through the design by analyzing device clocking and data information coupled with accurate cell timing models.
To minimize the number of paths for test generation, a subset of the most critical paths is accepted. Path information including launch and capture points and pins along the path, as well as transition information, are written to a file.
Utilizing the information from CPA, test-pattern generation tools can automatically generate critical-path tests, including initialization, transition launch, transition capture and propagation to an observable output. The ATPG tools are extended beyond the normal capability of functional stuck-at testing to meet the requirements of path sensitization and launch, and to perform capture sequences (two-clock tests).
Practical Considerations
Several practical considerations exist. First, because VLSI devices have so many paths, only a subset is selected for testing. This limits the capability to fully cover small and gross AC defects. General-purpose AC defect testing can be accomplished using a test generator capable of modeling delay or transition faults.
A second consideration is the path sensitization method. To ensure that a failure of a critical-path test will manifest itself if an AC defect lies along the specified path, a robust path test must be created. A robust path test is one in which the observed outcome of the test is influenced solely by a signal edge transition along the redefined path.
The ATE also imposes practical limits. In the actual manufactured device, the delay for a given path may be represented by a distribution. The decision of where to place the edge for the second clock will be based on the accuracy of the test equipment itself (to what degree of precision can the edges actually be defined) and the trade-off between defect detection and device yield.
If the second clock edge is set too low, good devices may fail. If it is set too high, failures may go undetected. Finally, the ATE may place limits on the total number of non-unique edges that may be set and may restrict the total number of testable paths.
Resulting Quality
These critical-path tests can be used in a variety of ways on the manufacturing floor. As a means of ensuring device performance at a rated speed, the test can be applied with a pass-fail approach.
Many companies use these tests to speed-grade devices. In speed grading, the measure point of the second clock (capture clock) will be set to a given value. If the components pass the test, they are binned or certified to a set maximum clock frequency.
The failing devices are retested with the capture clock timing relaxed. Repeating this process allows sorting of parts into lots based on maximum operating frequency.
Combining critical-path tests with functional stuck-at tests and even transition tests improves device quality levels. These critical-path tests identify small process variations that result in critical device-timing variations.
Utilizing automated test generation techniques coupled with CPA products provides a low-cost way to augment existing tests to achieve higher device qualities.
About the Author
Dave Hofer is the ASIC DFT Product Manager at Mentor Graphics Corp. He holds an E.E. degree from the University of Minnesota and an M.B.A. degree from Portland State University. Mentor Graphics Corp., 8005 S.W. Boeckman Rd., Wilsonville, OR 97070, (503) 685-7000.
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Copyright 1995 Nelson Publishing Inc.
September 1995
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