Many of us have bought a new automobile smug in the knowledge that we got a great deal. The smugness evaporated when we discovered that the low purchase price was more than offset by high repair costs or worse-than-expected gas mileage. Today’s knowledgeable car buyers make sure they understand all ownership costs before going into the showroom to get the best deal.
If only the same were true when we buy test equipment. Too often, buyers focus exclusively on the purchase price and pay too little attention to the operating costs down the road. This behavior is particularly ingrained in companies that have complicated capital budgeting processes where operating expense is often hidden in overhead budgets with little accountability.
In today’s highly competitive atmosphere, the era of worrying only about the purchase price of a tester is long past. Savvy test engineers have discovered that just a year of operating costs can outstrip acquisition costs. Manufacturing managers have figured out that test is a big element of total cost and that it needs to be attacked on many fronts simultaneously.
Consider a real-life example: A PC motherboard manufacturer bought a new in-circuit tester for $150,000. A test program bought from a third-party programming house cost $7,500, and a fixture for the board was another $5,000. It took just 12 test job sets to equal the tester’s purchase price—and that didn’t include operator costs, tester service costs, or charges associated with implementing design changes in the programs or fixtures.
It doesn’t take long to figure out that a truly low-cost tester is a lot different from a low-price tester. Achieving a low-cost test solution is more complex and requires focusing on a whole range of issues beyond the tester invoice.
Match the Tester to the Manufacturing Process
Before we address these issues, it’s worth noting that reducing the purchase price remains an important factor in trimming test costs. In the past 10 years, electronics manufacturers have spent far more money on testers than they needed to spend. This investment sitting in unused tester capabilities cannot be spent on new products or to enhance manufacturing productivity.
Blame can be spread evenly. Perhaps management did not encourage close communication between design and manufacturing and test functions. As a result, test managers bought “tester insurance” in the form of expensive, complex combinational testers to make sure they could test whatever boards the design group tosses over the proverbial wall. Capabilities like multiple timing sets and 10- to 20-MHz pattern rates, seemingly so critical before the purchase, are rarely implemented after the purchase because there’s not enough time before the next engineering change order (ECO) or the next board design comes along to demand scarce programmer resources.
The harsh competitive realities of worldwide manufacturing require that a rational circuit-board test strategy produce economic value by reducing manufacturing cost, improving product quality and shrinking cycle time. Achieving these almost mutually exclusive goals requires matching tester capability to exactly what needs to be tested—no less and no more—and buying only the capabilities you need and will use.
The tester’s productivity, fault coverage and reliability, rather than technical performance criteria such as pattern rate, pin skew and memory depth, are now the primary elements driving the success or failure of the board test strategy. As a result, lower-priced manufacturing process testers have replaced higher-priced combinational testers on many of the world’s most productive factory floors.
Modeling the Test Strategy to Understand Cost Sources
Not surprisingly, reducing overall test costs starts with understanding your manufacturing and test process. First, we create a simple model of the process, then we add economic variables to it. The basic Test Strategy Cost Model assumes that all boards pass through three distinctive stages (Figure 1):
1. Assembly Process¾ All manufacturing steps preceding structural test.
2. Process Test¾ The stage where boards are inspected for manufacturing faults. The model allows you to compare the costs of alternative manufacturing process testers and to make a direct comparison of the costs of alternative test strategies.
3. Final Test¾ All boards leaving the structural test pass through the final test stage. The model assumes that the final test stage is the “quality gate” that accurately determines if boards are good or bad, and that failed boards are correctly repaired; that is, all boards exiting the final test stage are good and final test yield = 100%.
The model also assumes that failed boards pass through a repair loop only once and that the tester determines them to be defect-free after being repaired.
Classifying Costs
While numerous ways to classify manufacturing test costs exist, a simple view puts costs into three areas:
Equipment cost.
Operating and application cost.
Escape cost.
Equipment cost is determined by tester productivity, the average time it takes for an average board to pass through the structural test stage. Along with raw test time per board, tester availability (uptime), the number of times an average board passes through the test-and-repair loop, handling time and operator efficiency determine test-process time.
If the assembly process generates boards at a rate of V boards per unit of time, and the structural tester has a throughput capacity of D boards per unit time, then the required tester capacity is V/D boards. As board volumes increase, users resist buying additional testers; instead, they focus on increasing productivity by improving other variables. Greater tester reliability, minimum handling time during which the tester is idle and, above all, higher tester throughput are the main improvements for reducing equipment cost.
Other significant equipment costs beyond the process testers themselves include repair benches and, most significantly, the number of final test stations required. Most final test stations consist of expensive instrumentation, particularly for communications products. The capital cost at final test is often several times the capital cost of the process testers.
Multiple final test stations are often needed because both verification and diagnosis at final test normally involve human intervention. Even with computer-controlled instrumentation, verifying correct board operation typically takes several minutes, and fault diagnosis can range from minutes to even hours to find subtle faults.
Operating and application cost is the expense of day-to-day tester use, such as training and placing operators in front of the tester if it’s not being used with automatic handling, maintenance, service contracts, repair parts or utilities. In today’s manufacturing environments, these traditional costs usually pale in comparison to application costs—the expense of developing test programs and fixtures and modifying them as ECOs occur. Test job development, particularly to meet the one- or two-week quick-turn requirements typical in high-pressure manufacturing, is costly both in out-of-pocket and opportunity costs.
Figure around $10,000 for a typical VLSI SMT board test job (program and fixture) such as a PC motherboard. Even with new CAD/CAE-to-fixture and program design tools, a manufacturer bringing on 25 or so new test jobs a year plus dealing with one or two ECOs per job will find applications cost to be the major test expense.
Escape costs, often called quality costs, are more than the costs of testing all good boards at final test. Bad boards “escape” from the process test stage and must be diagnosed at final test. The lower the yields leaving process test and arriving at final test, the greater the number of final test stations required since failed boards usually demand time-consuming manual diagnosis.
It’s easy to see how final test cost is driven strongly by the test coverage (or lack of test coverage) of the process tester. The more bad boards that must be dealt with at the final test stage, the more final test capacity—and cost—is required. If the structural tester fails to detect board faults, the faults must now be diagnosed at the more expensive final test stage. Escape cost is an indirect cost paid at final test, but incurred at structural test. The higher the structural test yield, the lower the escape cost.
How to Reduce Test Costs
Cost reduction cannot occur before cost comprehension. Only by understanding where the costs come from can we attack them. That means we need to understand exactly what we’re spending for what, as well as a host of other variables such as manufacturing yields, tester throughput, board volume and mix.
To be useful, an economic model should include sufficient assumptions to avoid having to collect data about variables that don’t matter very much, yet be robust enough to approximate reality on the manufacturing floor. A reasonable analysis may involve knowing 50 to 75 independent variables.
The economic model shown in the sidebar can be used to compare various test systems, as well as to rank cost elements, uncover the source of unexpectedly high costs and guide corrective action.
With a model in hand and a means of organizing cost sources, we tend to move directly to action, yet it could easily be the wrong cost-cutting action. Often, the temptation is to attack equipment cost first. Spend less capital, the theory goes, and we’ll be in fine shape. Yet, the tester purchase price often tends to be third or fourth in the Pareto cost order in many manufacturing environments. For example, in a low-volume operation that builds a large variety of very complex boards, test programming and fixturing cost will invariably dominate.
Another popular cost-saving means is continuing to deploy obsolete test equipment, but this typically results in higher per-board test costs with lower fault coverage because of the slow throughput and diminishing capability and reliability of older gear.
An economic model can help us make the right cost-cutting moves. By adjusting different variables, we can directly predict their effect on the costs we’re examining. Only through this approach can we understand how to find a truly low-cost test solution and shrink the cost of test.
About the Author
Craig T. Pynn is Marketing Manager at the Teradyne Assembly Test Division. He has published numerous technical articles and papers on board test and is the author of two books, Strategies for Electronics Test and The Low-Cost Board-Test Handbook. Mr. Pynn holds a B.S.E.E. degree from MIT and an M.B.A. degree from the University of California. Teradyne, Assembly Test Division, 2526 Shadelands Ave., Walnut Creek, CA 94598, (510) 932-6900.
SIDEBAR/figs (5)
The Test Strategy Cost Model
The Test Strategy Cost (TSC) Model is an interactive tool that enables you to calculate the total cost of a particular test strategy. The model takes into account the direct costs plus the indirect costs of test. The direct costs are incurred at process test. Indirect costs are attributed to defective boards that pass the process test and escape to final test, increasing overall test costs.
The model can be used to:
Calculate the total cost of a particular test strategy using a particular process tester.
Compare the total costs of different test strategies and different process testers.
Rank cost elements, uncover the source of unexpectedly high costs and guide corrective action.
The input data includes time frame and general financial variables, production data such as board volume and mix, tester-related information such as acquisition or maintenance costs, and application-related variables including programming or fixturing costs.
This TSC Model was developed by Craig Pynn at Teradyne. It is an Excel spreadsheet file available to you by contacting Teradyne at [email protected] or by calling 800-420-8456. The following panels show the required model inputs, explanations and results:
General Inputs caption¾
A
The Time Frame is the period over which you wish to do the analysis in integer years. For Total Labor Hours/Year do not consider shifts or shift differentials, since it is used for calculating employee compensation per year (2,080 h is default). The Burden Rate (%) is a multiplier factor added to raw labor rates to account for indirect expenses and overhead; enter 0 if you wish to perform the analysis ignoring burdened rates.
Production Inputs caption¾
B
The Total Annual Board Volume may represent the total number of all boards for the production environment you are analyzing. Or if you wish to perform the analysis across a single production line, enter volume and other production data as it applies to the single production line. The Scrap Rate is estimated as the percentage of the total boards that are eventually scrapped.
For the Fault Spectrum, the average defect rate per hundred boards over the entire mix is estimated for each of seven fault categories. The fault spectrum is assumed to be defects leaving the assembly process and entering the manufacturing process test stage; that is, the fault spectrum is the same for process tester alternatives. The model calculates process yield (first-stage yield) using the fault spectrum entered at this step.
Inputs for Process and Final Testers caption¾
C
In this section, enter variables for process tester alternatives. By entering data for alternative process testers, you obtain comparative data such as projected cost savings. By entering data for only one manufacturing process tester, you obtain noncomparative testing costs only.
Other Initial Costs should include all expenditures associated with implementation of the tester except fixturing and programming. For Throughput, enter good-board pass and bad-board fail and diagnose time for each process tester. The failed-board time includes whatever time is required to perform failed-board diagnostics on the tester. For most in-circuit testers, this is negligible, meaning that good- and bad- board test times are usually the same.
The Process Tester Fault Coverage is the estimated fault coverage for each fault class, as expected for each of the process testers. The fault categories are the same as the ones in the fault spectrum entry. The model calculates first-pass test yield (Yt) for each manufacturing process tester based on its respective fault coverage.
Test Fixturing/Programming Costs caption¾
D
For Programming Time, enter the average number of hours you estimate are required to develop an acceptable production-level process test program for each of the alternative testers.
Results Worksheet–last in series, does not have a caption¾
E
Copyright 1996 Nelson Publishing Inc.
June 1996