Automated test equipment is a major investment that can return handsome benefits. Some benefits, though, may not be obvious, especially those derived from information that automated testing provides about manufacturing processes.
Achieving these benefits is a matter of acquiring equipment with the appropriate specifications. This seems to be the case for automated parametric testing (APT) systems used by semiconductor fabricators. The lessons learned in this industry can be applied to many types of automated test-equipment purchases.
Parametric Data Base
The use of APT during manufacture of semiconductor wafers is crucial in controlling process yields. Semiconductor fabricators (fabs) rely on this form of work-in-process testing to provide from 70% to 90% of the data needed to maintain control of existing processes and to rapidly reach acceptable yields in start-up situations.
Beyond development and control of processes, a fab’s parametric data base is used by process engineers, product development engineers, circuit designers, reliability engineers, fab managers, and of course, test engineers (Figure 1). These engineers rely on the data to help refine established processes, the design of specific devices, circuits and completely new products and processes.
APT systems measure electrical properties of special test structures placed on semiconductor wafers. The test structures may be “drop-ins,” which are located where functional dies would normally be placed. Or the test structures could be placed in wafer scribe lines, which are lines between functional dies defining diamond saw cuts that separate finished devices.
The latter scheme saves potentially useful wafer real estate for functional devices. On the other hand, using drop-ins greatly increases the opportunity to expand the number of test structures, which can provide a more thorough evaluation of the process.
A test structure is a proxy for an actual semiconductor device. It must be designed so that, when probed and electrical measurements are taken, it reveals variations in fab processes that could affect device yields, performance or reliability. Since there are many different processes leading to a finished die, many types of test structures and test algorithms are needed, and each must be designed for a specific type of device and step in the fab process. As a result, parametric testing is conducted at multiple locations in a fab processing facility.
Although parametric testing can be done on finished wafers, testing that monitors front-end processes continues to grow. Front-end processes typically fall into either of two areas: front-end-of-the-line (FEOL) or back-end-of-the-line (BEOL) processes.
While these definitions are not precise, FEOL generally refers to processes in which transistors and capacitors are formed, along with the polysilicon gate layer. BEOL processes include all the steps used to form metal interconnects and associated dielectrics.
Figure 2 illustrates a typical CMOS cross section as it exists after several FEOL and BEOL processing steps. The cross section represents actual devices and test structures.
In both FEOL and BEOL areas, the trend is to test earlier to determine whether the wafers should be allowed to move on to the next process step. Early testing reduces costs by preventing further processing of wafers with out-of-tolerance parameters. It also helps highlight sources of processing problems more quickly.
Test structures on the wafer are often probed and tested after each BEOL metal/polysilicon insulation layer is added. Each BEOL test suite can consist of the types of measurements shown in Table 1, which are typically DC or low-frequency AC measurements.
ROA Model for APT Systems
As semiconductor device dimensions continue to shrink and the costs of constructing fab facilities escalate, the demands placed on parametric testing are also growing. Fabs are seeking APT systems with higher performance that will help supply these benefits:
Shorter ramp-up time on new process lines.
Improved yields.
Greater product throughput.
Increased utilization of production facilities and equipment.
Better product performance.
Lower cost and/or higher payback from test-equipment ownership.
When considering the acquisition of a new APT system, these complex demands require some sort of Return On Assets (ROA) evaluation. This should include an objective analysis of the costs and potential payback of such a purchase. The primary factors to consider are product-related benefits, the benefits of better process information, and the costs associated with owning the APT system.
Product-related benefits are those associated with replacement or improvements that result in better products or more efficient testing. An evaluation of process-related benefits attempts to put an economic value on better information about the process. Cost of ownership should be based on total life-cycle costs, including installed equipment costs, software costs, ongoing cost of operation and maintenance costs.
Table 2 is a sampling of benefits derived from adding a new parametric tester or replacing or upgrading older equipment with the latest generation of APT systems. Many of these benefits can be realized only if the new system is capable of more types of tests and more sensitive tests, and performs them faster.
New APT Systems
Besides these capabilities, new APT systems must deal with the realities of a deep submicron fab facility. Deep submicron CMOS devices, which have dimensions of 0.35 micron and less, require APT systems that provide sub-picoamp sensitivity along with increased speed to allow more testing (Table 1).
For these devices, the performance of some APT systems is marginal, at best, because of their fundamental test approach. Typically, this approach uses multiplexed instrumentation connected to pins that make contact with the DUTs. This arrangement most likely uses an array of source and measurement instruments, a reed-relay switching matrix, long cables, and a probe card to connect tester cables to DUT pads on the wafer.
Inherent drawbacks to this type of APT system design include accuracy and sensitivity limitations due to capacitance and resistance associated with the cables, interconnects and the reed-relay matrix. Speed also is limited because of the high dielectric absorption and parasitic capacitances associated with these system components, particularly when making current measurements at the picoamp level. Even with state-of-the-art guarding techniques, it takes time for matrix reed switches to settle to a steady-state level before an accurate measurement can be made.
APT system manufacturers are addressing these issues with new designs that shorten or eliminate cabling that formerly carried low-level signals. One design uses a test head with active electronics for each of the probe pins (Figure 3). This type of design is analogous to per-pin electronics now used in functional testers. The test head amplifiers are within 10 cm of the DUT and each pin can be driven by its own bias voltage supply.
This design reduces the capacitive load on the measurement circuit node by eliminating test-head cabling and minimizing other interconnects. As a result, gate oxide and interlayer dielectric capacitance measurements below 1 pF are more accurate. By moving the switching matrix to the instrumentation side of the pins and using solid-state switches, settling times on low current measurements below 10 pA are faster. Overall, speed and sensitivity can be improved by an order of magnitude.
Test Structures
Regardless of the speed and sensitivity of an APT system, the wafer electrical data collected must correlate with critical process parameters. To get the most out of an APT system, the system designer, fab test engineers and process designers must work together when creating test structures and programs. Once process engineers establish a correlation between wafer electrical parameters and key process parameters, test engineers and APT system designers can:
Design physical wafer test structures that allow measurement of these electrical parameters.
Create parametric test suites and algorithms that collect pertinent data and characterize the wafer in terms of these parameters.
By designing the hardware, software and test structures in concert with each other, many improvements are possible. These include greater insight into fab processes, higher test throughput and lower test-system complexity for equipment operators and test engineers.
Software Boosts ROA
Other ROA enhancements are built around modular test-development software designed for a wide range of needs (Figure 1). Typically, modularity is achieved with dynamically linked libraries (DLLs). These DLLs contain drivers for the most popular wafer probers. There also are high-level subroutines and source code for characterizing specific types of semiconductor devices.
With modular DLLs, you do not have to go through a full-blown program development cycle (write—compile—link—run—edit) to make small program modifications. Instead, you can run and debug new test-program components instantly inside a program editor, line by line if desired. Features such as these reduce program development, debugging and startup times associated with new lines and expanded parametric testing.
Another type of software that complements APT systems is finding increased use among fabs. It is a yield-management data base that, in the past, was tailored for the collection of defect data. Now, its use includes data from other areas of the fab, including APT system data.
All of these changes are now taking place in new APT hardware packages with smaller footprints, greater measurement integrity, increased reproducibility, higher throughput and better reliability. The net effect is higher equipment utilization, lower cost of test equipment ownership and a quicker return on assets.
About the Author
Gary Pinkerton is Director of Marketing for the Semiconductor Business Unit at Keithley Instruments. Before joining Keithley in 1987, he was with Hewlett-Packard and held a variety of engineering and marketing positions with both companies. Mr. Pinkerton holds bachelor’s degrees in economics and electrical engineering from Harvey Mudd College and an MBA degree from Colorado State University. Keithley Instruments, 28775 Aurora Rd., Cleveland, OH 44139, (216) 248-0400.
Test
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Description
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Qty
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Measurement Level
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Structure
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1
Opens and Shorts
Test for open pads and shorted gates
3
Site Pads
2
Leakage Currents
Gate leakage, test isolation, device leakage in off mode-drain to source
33
5-140 pA
Scaled MOSFET
3
Ids
Drain current with known gate, drain and substrate voltages
16
20 mA
Scaled MOSFET
4
Vt
Threshold voltages: w/maximum transconductance, in saturation, for field device p and n channels, etc.
46
0.2 to 12 V
Scaled MOSFET and Field Transistor
5
Rds
Vds / Id at specified Id and Vgs
20
25 to 100 W
Scaled MOSFET
6
subVtslope
Sub-threshold slope of drain current vs. gate voltage
20
< 10 pA
Scaled MOSFET
7
peakIsub
Peak substrate current
6
5 µA
Scaled MOSFET
8
res2t
Determine resistance value using 2 terminal connection
21
2 to 1 k W
Resistor
9
diodefvmi
Diode characterization, force a voltage, measure current
2
10 nA
Diode
10
bv
Breakdown voltages: diodes and from drain to source, gate grounded
12
3 to 10 V
Diode
11
res4t
Determine resistance value using 4-terminal connection
11
2 to 1 k
W
Van Der Pauw
12
Tox
Capacitance to determine gate oxide thickness
2
10 to 100 pF
MOS Capacitor
Â
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Product-Related Benefits
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Process-Related Benefits
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Reduced cost of product testing
Greater insight into the process through increased sampling/test data
More dependable devices by adding wafer level reliability testing
Better process information due to increased measurement sensitivity and data integrity
Improved product performance/sales value from better design-related data
Tighter process controls
Cost reductions from not shipping bad product
Quicker qualification of new processes
Increased revenue from not rejecting good product
Yield improvements
Copyright 1996 Nelson Publishing Inc.
September 1996
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