The multimedia extension (MMX) is captivating the imagination of the PC market. The integration of high-resolution graphics, video compression and decompression, and CD quality sound onto inexpensive chip sets provides the incentive for consumers to buy the newest generation of PCs.
To catch this buying wave, PC manufacturers must continue to meet the consumer’s $2,000 price point. This means that the MMX chips must be inexpensive to build and to test. Yet these chips must move and process massive amounts of data in real time, requiring high data rates and wide buses. Recent advances in fabrication and packaging technology have made these devices possible.
Today’s smaller-geometry manufacturing processes provide higher levels of integration with a lower manufacturing cost per die. Now it’s going to take a revolution in test technology to bring these new devices to market.
Why will it take a revolution? Because higher-speed ATE pins cost too much when built using the same technology as before, yet MMX bus speeds are approaching 200 MHz and clock speeds are several times faster than that.
Devices already are smashing through the 512-pin barrier, and will soon reach 1,024 pins and more. Yet high pin-count ATE is too bulky and difficult to interface to handlers and probers unless dramatic steps are taken. Such revolutions typically come at a high cost—the cost of complete retooling to a new programming language, DUT boards, interfacing mechanics, spares, facilities, and training.
Here’s what to look for in the newest generation of ATE to eliminate most of these costs to bring revolutionary performance to market at an evolutionary price tag. For each major element of an ATE digital channel, there is an optimum IC technology that offers the best combination of density, power consumption, and speed. Recent advances help high-density technologies to be used in areas never before possible, as shown in Figure 1.
MOS DRAM Vector Memory and CMOS Memory Controller
MOS DRAM is the right vector-memory technology because of its high density, low power consumption, and faster progression along the technology curve. However, it is slower than SRAM and also must be refreshed.
To address these problems, the ATE vendor must borrow from microprocessor technology. Adding a CMOS memory controller with fast cache memory and hardware- refresh control provides real-time operation while hiding refresh cycles. By arranging the memory in sufficiently wide words, slower DRAM can be interleaved to provide the same effective data rate as faster SRAM.
The memory controller reads in the slower, wider data and outputs it as a faster, narrower data stream. The use of CMOS in the memory controller also provides the high density needed to incorporate a fast SRAM cache memory on chip so the controller transparently buffers vector data during address jumps.
CMOS Formatting and Timing
ATE must deliver extremely accurate timing edges that are stable regardless of temperature or format. ECL is the traditional technology of choice to meet these requirements. However, ECL is a high-power, low-density, and costly technology poorly suited to the demands of high pin-count ATE.
Fortunately, CMOS stabilized technology now has the same high accuracy and stability as ECL, making it the technology of choice. By applying on-chip regulation of temperature and voltage bias, CMOS delivers the high stability of ECL in a high-density, low-cost process technology.
CMOS or GaAs Pattern Control
Simple pattern execution, such as executing linear vectors with repeats, is accomplished easily using high-speed ECL. Since most CAD-generated vectors are this type, this is the minimum requirement for IC testing. However, there are issues that argue strongly for more complex pattern control.
The first issue is the amount of vector memory. While repeats offer the first level of vector compression, today’s large MMX chips require long patterns that still can consume a lot of memory. With the addition of looping and subroutining capability, patterns can be compressed more, and memory size and expense can be reduced.
The second issue is the nature of MMX itself. Because MMX chips are designed to operate with video, audio, CD, DVD, and hard disks, many of the patterns they need are, by their very nature, highly repetitive.
Video data, for instance, is organized into pixels, lines, and frames. Each line contains so many pixels, and each frame contains so many lines. Such sequences are easy to encode and decode with more complex pattern opcodes like loops and subroutines. These highly algorithmic patterns are still commonly created by hand, which is much more convenient using complex opcodes.
The third issue involves the presence of analog cells on MMX devices. ICs that include integral analog-to-digital converters (ADCs) and digital-to-analog converters (DACs) are increasingly common. These ICs process and generate real-time signals and cannot tolerate reloads or interruptions in data flow. This requirement dictates that all pattern-control opcodes function without any sort of wait state or time insertion.
The task of generating complex opcodes without time insertion taxes ECL technology. While it can be done, the complex circuitry results in a large circuit board running at very high speed and at very high temperature.
GaAs is a better technology for this application, delivering speed similar to ECL at typically only one-half to one-third the power consumption per gate. CMOS is better still, consuming less than one-tenth the power of ECL at typical operating frequencies. The choice of CMOS or GaAs depends upon the operating frequency and the details of the design. CMOS has the most attractive density, while GaAs has the most attractive speed. Either technology can dramatically shrink the space and power needed to provide the complex pattern control needed by MMX.
Mixed-Technology Pin Electronics
Today’s ICs typically operate from either 5-V or 3.3-V supplies, while chips a few years from now will run on as little as 1 V. ATE pin electronics must cover all of these ranges while delivering the high edge rates and wide bandwidths needed for MMX. Typically, it takes a mix of technologies to create pin electronics with the needed capabilities.
The most demanding element in a pin-electronics design is the comparator, which must simultaneously achieve high bandwidth and high sensitivity. This requires a high-frequency process that delivers maximum transconductance. Bipolar technology excels in this application, and is the obvious choice for building high-performance comparators.
Pin drivers are a different story. They must provide fast and stable switching time, a stable 50-W output impedance, and voltage sufficient to drive the DUT.
Pin drivers do not provide an opportunity to achieve dramatic improvements in either density or power consumption. They must drive the same voltages through the same low-impedance transmission lines, delivering the same power to their load no matter which technology is used. Therefore, either CMOS or bipolar technology provides the needed performance for MMX at about the same cost.
Other pin-electronics elements extend the mix of technologies. For instance, active loads typically are implemented using Schottky diode bridges, while reference levels frequently are implemented using CMOS DACs.
Plumbing
With the requirement to package two to three times as many channels operating at double the data rate into the same size test head, cooling has become one of the critical technologies for today’s ATE. Since pin-electronics technology offers little opportunity to reduce power consumption, any ATE design must deal with increased heat as the number of pins inside the test head doubles. By and large, this means that air cooling is no longer adequate, and some form of liquid cooling must be used.
Designs that still employ ECL for formatting or timing often must locate such circuits in a large mainframe, where they can be kept at a low enough density to cool. Frequently, the difficulty of conducting the heat away from fast ECL devices requires that coolant be plumbed onto each PCB and routed individually to critical areas. The plumbing must be disconnected when boards are being serviced, presenting a danger of leaks and spills. Such systems tend to be messy, difficult to service, and costly.
CMOS designs, however, run cool enough to be placed right in the test head with the pin electronics. With the cooler CMOS designs, it still is practical to contain the coolant in a simple closed-loop system to which the PCBs mount mechanically. There is no need for plumbing on the PCBs, and there never is a risk of spills during service. The cooling design becomes clean, simple, and relatively inexpensive. This simplification of the cooling system is illustrated in Figure 2.
Cabling
Cabling continues to be one of the most fragile and least-reliable elements of ATE. Unfortunately, cables are bound by the laws of physics and the properties of materials, making only incremental improvements possible in their physical size. Two types of cabling dominate today’s ATE: power cabling and time-critical cabling.
Power Cabling
Power cabling provides the raw energy to all of the tester electronics. While not as fragile as time-critical cabling, power cabling tends to be bulky. This becomes particularly critical in the design of the test head, where power wiring consumes valuable space that otherwise could be used for electronics. Low-power CMOS ATE designs are preferred because they require fewer and smaller power cables, resulting in smaller test heads and more reliable connections.
Time-Critical Cabling
Time-critical cabling carries signals between the timing generators, formatters, pin electronics, and the DUT. Once the timing edges have been generated, the propagation delay must remain absolutely stable, predictable, and immune to crosstalk all the way to the DUT.
This type of cabling is critical for ECL designs, where the timing generation and formatting often are located in a mainframe while the pin electronics are in the test head. Coax or differential twisted pairs are required for these time-sensitive signals. These cables can be mechanically fragile, and their number increases with pin count.
The best approach to simplifying time-critical cabling is not to have it at all. By using low-power CMOS IC technology, all timing, formatting, and pin-electronics circuits can be located on one PCB, eliminating the need for such cabling altogether. Figure 2 shows how much simpler the cabling of a single board design can be.
True Compatibility
ATE customers have made a large investment in their existing systems: programs, DUT boards, and training. Successful new products must carry this investment forward, providing new performance with little more customer investment than an evolutionary product requires. Look for compatibility in these areas:
Programs and DUT Boards
Basically, there are two approaches to moving older products onto newer testers. The most common approach is translation. By translating a few high-volume programs, new ATE can be kept productive until enough new devices have been introduced.
With translation, an existing program and DUT board are used as models to create a new program and DUT board. The program is rewritten to reflect the differing capabilities of the two machines, and the DUT board is redesigned with the proper form factor and electrical interfaces. Because translation takes significant time and skill, it generally is only practical for high-volume devices.
The second, more difficult, approach is full compatibility. The new tester must accept existing DUT boards and run existing programs without modification. While this sometimes is achieved for successive models from a single ATE vendor, it is a very tall order when a model change delivers a large leap in performance.
Even so, systems that achieve this level of compatibility save many man-years of translation investment. For those companies with a high mix of lower-volume devices, it may be the only practical alternative.
Positioning and Docking
More ATE manufacturers are incorporating integrated test-head manipulators into their system designs. This eliminates the extra footprint required by a free-standing manipulator, and keeps test-head cables off the floor and out of harm’s way.
Good designs preserve the full range of motions available in free-standing manipulators: translation and rotation in X, Y, and Z. Look for this feature and for the range of motion that allows the head to interface to your selection of handlers and probers.
Be sure that the test head fits underneath the lowest handler and on top of the tallest prober. Also check the ease of achieving a hard dock between the test head and the prober or handler. Does it bind? Does it require a lot of force? Smaller, CMOS- based test heads are compatible with all of today’s popular probers and handlers and are easy to interface. Many larger test heads are not.
Tools
Like a skilled cabinetmaker, you rely on your tools. You learn their strengths and weaknesses, and when best to apply each one. They become extensions of you, multiplying your efficiency.
Since retraining to a new set of tools takes time, the best situation is to stay with the tools you know. This can be achieved by adopting an ATE that offers a tool suite you already use.
However, if you must use a different set of tools, they should be graphical and intuitive for immediate productivity. An example of a modern graphical tool is the DataScope tool, or DSTool, illustrated in Figure 3. With DSTool, you have a virtual logic analyzer that displays programmed, expected, and actual waveforms for any selection of pins at any point in a pattern.
Conclusion
The emerging explosion of MMX microprocessors and 3-D graphics, DSPs, HDTV, DVD, and HDD processors requires ATE offering a thousand pins operating at 200-MHz data and even faster clocks. The latest in high-density IC technology is needed to achieve this revolutionary performance.
CMOS IC technology, in particular, provides the unique combination of high accuracy, high density, and low power so that complete high-performance pin channels can be built on a single PCB. This, in turn, reduces expensive and failure-prone electrical cabling and exotic plumbing.
And the resulting space savings remove the barriers to compatible DUT boards and mechanical interfaces. A modern MMX system architecture, illustrated in Figure 4, is simpler, less expensive, and more reliable. Its modularity allows the pin-count to meet even more demanding requirements. CMOS solves the MMX test dilemma of high performance at low cost.
About the Author
Jim Seaton, a product manager at Credence Systems, has spent 13 years with the company in engineering and marketing. He previously was employed for 13 years at Teradyne as a design engineer and engineering manager. Mr. Seaton holds a B.S.E.E. degree from the Massachusetts Institute of Technology and an M.B.A. degree from Boston University. Credence Systems, 215 Fourier Ave., Fremont, CA 94539, (510) 657-7400.
Copyright 1997 Nelson Publishing Inc.
July 1997
|
|