Most IC designers today know that using design-for-testability (DFT) techniques almost always results in higher quality output and faster time to market. Higher quality because better insight is gained into the IC’s entire functionality since it is more fully testable. This decreases the likelihood that marginal ICs will end up in finished products. Faster time to market because device performance testing and program preparation times are shorter.
Many design specifications now include firm testability goals. Meeting these goals within time constraints is made difficult by two factors: the complexity of today’s ICs, and the impracticality of designing first and adding testability later.
The only practical solution for today’s large ICs is to add one or more types of test structures and initiate DFT insertion and basic IC performance design concurrently. However, for all but the most trivial designs, manual insertion of DFT structures is time- consuming, and automation of this process is essential. Just as computer-aided engineering (CAE) tools have long helped to speed the basic design tasks, so can DFT analysis and insertion tools help provide the needed testability.
“Many automated DFT insertion tools, such as those providing full-scan insertion, have matured to being almost push-button,” said Michelle Kuyl, technical marketing engineer at Mentor Graphics. “EDA tools that insert boundary scan provide a relatively low-cost solution to a routine and yet time-consuming task. Tools that insert boundary scan at the register transfer level (RTL) design stage bring even greater benefit.
“Built-in self test (BIST) insertion tools, if flexible in the supported architectures and algorithms, provide a quick way to add testability and reduce tester time and memory requirements. These tools can trim weeks or even months off the IC design cycle time,” Ms. Kuyl concluded.
While DFT structures are added at the IC level, they also provide benefits for higher assembly and system-level tests. The degree to which tapping into IC-resident DFT resources can help test and diagnosis activities at higher levels depends on two factors: the test equipment’s capabilities and, more importantly, the test engineer’s familiarity with the DFT techniques used.
Boundary Scan Insertion Tools
Boundary scan facilities, as defined in the IEEE 1149.1 (JTAG) standard, now are included in many mass-produced devices, such as Intel’s Pentium and Motorola’s PowerPC; PLDs from AMD, Altera, and Xilinx, and TI’s DSPs. Preconfigured boundary scan cell and test access port (TAP) controller libraries also provide ready-made structures that can be incorporated into ASIC designs.
Initially used for interconnect testing, boundary scan access facilities now are being used for in-situ programming of PLDs and initiation/readout of internal scan tests and device-resident BIST. Almost all companies providing DFT tools offer automatic boundary scan insertion and test-generation tools.
Examples of these tools are Mentor Graphic’s BSDArchitect™, Lucent Technologies’ ATTDFT/BCAD and Sunrise’s START™ tools. JTAG Technologies and ASSET InterTech provide boundary scan test-program generation and diagnostic software and hardware as well as scan access-based software packages to facilitate on-board programming of PLDs.
A typical automatic boundary scan software tool set, such as Sunrise’s START, inserts and stitches a user-defined TAP controller and boundary scan I/O cells into a given design. The tool also uses its knowledge of the TAP instructions to extract a state transition diagram and verify it against the IEEE specification. Then it generates sequential test vectors. Finally, the tool automatically creates a boundary scan description language (BSDL) profile for use with circuit-board test tools.
Full Scan
Automatic test-program generation (ATPG) software tools generate highly effective test programs in minimal time for combinational logic circuits but not for sequential logic. A DFT technique, referred to as full scan, alleviates this problem by adding circuitry to temporarily reconnect all sequential elements (flip-flops) into one or several shift registers.
When placed in a test mode, zeros and ones are shifted through the resultant registers, supplying a simple test for assessing the functionality of all flip-flops. The register elements also provide added test access to the combinational logic, again improving circuit testability.
To achieve this implementation, the nonscan flip-flops are replaced with scannable flip-flops, and the scan inputs and outputs are connected in a chain. “In 95% of today’s full scan designs, this insertion is done automatically,” said Mark Milligan, vice president of the Test Business Unit of Viewlogic at Sunrise. “The benefit of full scan is a predictable DFT process with high fault coverage and fast ATPG run times.
“But the scan insertion must be handled intelligently, taking design hierarchy, multiple clock domains, and circuit behavior into account to ensure correct scan-chain test operation,” Mr. Milligan warned. “For example, timing problems can exist within the scan chain at areas where it crosses different clock domains. One common way to deal with this problem is to place a data lockup latch in the scan chain at the clock domain interface.”
Partial-Scan
When performance requirements or silicon-area constraints make it impractical to implement full scan, only some of the flip-flops are replaced by scannable sequential elements. The selection of circuit parts to be made scannable then is based on a functional partition or an area-optimization-driven approach.
The functional partition approach might implement full scan in the control-logic section and no scan in the data path of the design. This would prevent added delay in the timing-critical data path, but take advantage of timing slack in the control-logic to provide adequate coverage.
In an area-optimized approach, generally used when the silicon area directly relates to end-product costs and profits, a large amount of circuitry may be left inaccessible. This increases the computational tasks for ATPG.
“Fortunately, sequential ATPG lends itself to distribution across multiple workstations for parallel execution,” said Mr. Milligan. “A 100,000 gate design using an area-optimized approach may require two days of ATPG run time. But when networked over four workstations, only an overnight run is required.
“In an area-sensitive scenario, the design engineer may fault-grade an initial set of functional test vectors with our FaultSim™ tool to identify detected faults. Next, START uses the detected fault list to select and insert the minimum additional test logic. Finally, TestGen™ generates additional test vectors to satisfy the engineer’s fault coverage requirements,” Mr. Milligan concluded.
Full-scan and partial-scan implementations are circuit-configuration dependent, and until very recently, could not be automatically defined and added at the hardware description language (HDL) design level. Now they usually are woven into a completely defined circuit at the gate level. Tools that accomplish this task and perform ATPG include Mentor Graphic’s DFTAdvisor and FastScan™, Sunrise’s START and TestGen, Lucent Technologies’ ATTDFT/GENTEST and ATG Technology’s INTELLECT software.
INTELLECT performs low-impact partial-scan insertion. “Conventional full scan and partial scan require compliance with numerous design rules to ensure reliable scan shifting,” said Sean Morley, vice president product engineering at ATG Technology. “However, our isolated partial scan technique does not require a test-rules check. It fully automates the partial scan location and performs the netlist modification process to guarantee functional equivalence with the original design. The traditional problems of gated clocks, derived clocks, and derived asynchronous sets/resets disappear.”
BIST Insertion
BIST circuitry, which usually consists of a test-pattern generator, a test-result evaluator, and control logic, helps an IC to test itself without external resources. While full scan is the most mature technology and provides maximum test coverage, BIST has long been talked about—but only recently found extensive support. It now has become essential since many consumer ICs and ASICs contain embedded memories or proprietary logic blocks that require special test stimuli or that are not easily accessible from external ports.
“Memory faults, for instance, differ from those encountered in random logic, so memory test requires its own solution,” said Ms. Kuyl of Mentor Graphics. “Algorithms, such as March tests, provide excellent fault coverage in a short test time, and they lend themselves well to being implemented on-chip, without consuming substantial area overhead.
“Embedded cores and blocks, often supplied by third parties, also are ported to and embedded in many designs,” Ms. Kuyl continued. “The need to protect intellectual property, as well as guarantee the quality of these blocks, makes BIST an attractive methodology in this situation. With BIST, the core is delivered test-ready, without the need to supply the design netlist for scan insertion and ATPG.”
When BIST is added to logic-circuit entities, it may not innately provide complete stuck-at or bridging fault coverage. However, it offers a more thorough test of timing-related performance since it runs at the device’s operational real-time rate. The penalty for implementing BIST is additional silicon area and design time.
Fortunately, new automated insertion tools accepting inputs in HDL simplify the BIST insertion task. “The typical IC/ASIC design flow starts with HDL and ends with a layout after passing through gates and transistor-level netlists while undergoing various types of logic and timing verification,” said Dr. R. Chandramouli, director of Silicon BIST Marketing at LogicVision.
“BIST and boundary scan structures can be defined in HDL, and can be automatically inserted at the HDL-design-level using CAE tools. This minimizes the effort and results in fewer design debug and design verification iterations than when introducing BIST at the circuit-level stage,” he continued.
Design synthesis tools that address BIST implementation, plus full- and partial-scan insertion to varying degrees, at the HDL level include MBISTArchitect and LBISTArchitect from Mentor Graphics, Design Compiler™ and Test Compiler™ from Synopsis, and ICBIST from LogicVision.
“ICBIST includes technology for automating BIST for embedded memories, logic, and boundary scan during the front-end design process,” explained Dr. Chandramouli. “The automation part of ICBIST inserts the necessary structures at the RTL level (in Verilog or VHDL) and generates a new synthesizable RTL model embedded with the test structures. Using ICBIST, the entire IC can be self-testing.”
Tool Selection and Benefits
When selecting DFT insertion tools, first determine whether they support the intended methodologies or architectures. “For example, if a designer wants to use a particular type of scan methodology, such as clocked scan, there will be no benefit from a DFT insertion tool that does not provide this capability,” commented Ms. Kuyl. “Another example might be a designer trying to create a BIST structure that applies a March C+ algorithm in parallel to two memories by using a tool that does not support either the algorithm or parallel application.”
Other selection criteria include the certainty that the DFT insertion process does not violate functional design constraints and operates within the user’s high-level design flow. The latter requirement, as defined by David Hsu, technical marketing manager of Test Synthesis at Synopsys, calls for these capabilities:
Providing analysis, synthesis, and verification at any hierarchical design level, from the block, to submodule, to the top level.
Handling designs with blocks at different stages of completion; for example, some blocks in RTL, others mapped to gates, and the rest as reused modules or intellectual property blocks.
Enabling the user to preview any specified DFT configuration without synthesizing any logic.
DFT detractors have focused on potential penalties, such as loss of silicon area. But it now is commonly recognized that while DFT investments are made at the IC level, benefits are realized at all subsequent stages.
“Boundary scan, incorporated at IC input/output ports, for example, provides benefits during manufacturing tests and for field diagnostics,” commented Shianling Wu, technical manager of IC Test Technologies and Tools at Lucent Technologies. “BIST can be used and reused at IC, board, and system tests.
“Other key benefits include high product quality and reduced test development time. All in all, DFT, automatically inserted with today’s tools, provides outstanding value,” Ms. Wu concluded.
Design for Testability Products
High Fault Coverage Achieved
Without Design Restrictions
The INTELLECT ATG System Software automatically generates high-fault- coverage test vectors and inserts required circuit testability modifications into ASIC designs. It uses a proprietary Isolated Partial Scan technique and operates in conjunction with industry-standard fault simulators, such as Verifault-XL™ and SILOS III™. The system does not impose limiting design-rule restrictions. Inputs are obtained from a Verilog source, outputs are a vector stimulus/response file, and a netlist includes inserted IPS modifications. $78,000. ATG Technology, (201) 236-3635.
Module Facilitates Testing
Nonboundary Scan Circuits
The Serial Test Extension Module (STEM) extends the boundary scan test capability of the ASSET Diagnostic System to devices or device clusters that are incompatible with boundary scan. STEM controls and observes test signals at connectors or physical access points by providing boundary scan input/output facilities. A basic STEM tester consists of a chassis with three channel cards providing 288 bidirectional channels controlled by boundary scan. By adding cards, STEM extends to 960 channels. From $7,975. ASSET InterTech, (972) 437-2800.
Comprehensive DFT Provided by
Memory BIST, Logic BIST Tools
MBlSTArchitect™ and LBlSTArchitect™ provide automatic insertion of BIST logic into ASIC designs. The products generate RTL Verilog or VHDL descriptions of memory test and BIST logic for interconnected multiple memory arrays and logic entities. An HDL test bench can verify the design using the company’s or other industry-standard Verilog or VHDL simulators or synthesis tools. MBlSTArchitect supports multiple algorithms and parallel application of test patterns. Floating license for MBlSTArchitect: $55,000; LBlSTArchitect: $75,000. Mentor Graphics, (503) 685-7000.
(MBlSTArchitect) no pix
Graphical Access Tool Added
To Test Generation Suite
DFT Explorer is a graphical access and exploration tool for the company’s Sunrise TestGen Software. It provides intuitive point-and-click selection and concurrent viewing of interrelated testability, fault coverage, and simulation information in two environments. A simulation environment includes three windows for graphical examination of data returned by the logic and fault simulator plus a hierarchy browser window which combines tree and outline style features. A testability environment contains two windows for concurrent browsing of testability and fault data. From $20,000. Viewlogic Systems, (508) 480-0881.
PC-Based Software/Hardware
Facilitate Boundary Scan Test
A range of hardware and software products helps users implement and perform boundary scan test. Hardware choices include the PC parallel-port-driven PM 3705 Explorer, a PC ISA or PCMCIA interface card, or the GPIB-based PM 3720 VectorBlaster. Test-oriented software consists of the PM 3770-22 BTPG™_I Boundary Scan Test Program Generator for Infrastructure and Interconnects, the PM 3770-23 BTPG™_C Boundary Scan Test Program Generator for Testing Clusters, the PM 3773 MTPG™ Memory Test Pattern Generator, the PF 2170-series VIP Vector Interface Package, and the PM 3790 BSD Boundary Scan Diagnostics Software. Hardware: from $1,500; Software: from $4,500. JTAG Technologies, 011 31 40 295 08 70.
BIST Tests Memories At-Speed
In Hierarchical Assemblies
memBIST-XT™, a BIST tool for boards and systems, is used to apply BIST technology to memory structures in PCBs, MCMs, and other hierarchical assemblies. The BIST controller, created at the RTL level, is configured automatically and resides on either an FPGA or an ASIC that is interfaced with the target memory. Approximately 1,000 gates are required to implement the controller. memBIST-XT includes BIST-controller and controller-interface (collar) logic and automation software. $20,000. LogicVision, (408) 453-0146.
Copyright 1997 Nelson Publishing Inc.
September 1997