The exploding demand for more complex ICs at lower selling prices has created the need for semiconductor manufacturers to reevaluate traditional test methodologies—which can account for 6% to 15% of a chip’s manufacturing costs. A very simple economic model that demonstrates the cost of test is based on the buy rate, the ratio of global, annual ATE revenue to global, annual semiconductor revenue (Figure 1). For the last 18 years, this ratio has stayed within 3% to 5%. In other words, 3% to 5% of the semiconductor revenue every year is spent purchasing capital equipment for external testing.
This buy rate is the average of all semiconductors, including memories, low-end chips, and high-end chips. The rate for high-end ASICs is most certainly higher. Also factor in the multiplier effect of at least two to three times on every dollar spent on ATE purchases to include the cost of test engineering, maintenance, and operational expenses. This makes the actual cost of test 6% to 15% of the semiconductor revenue.
As a percentage of the chip’s manufacturing cost, test cost will be higher. As a result, the consumer industry can increase its gross and net profit margins significantly by lowering the cost of test.
Design for test (DFT) techniques, such as scan, JTAG/1149.1, and automatic test program generation (ATPG), have helped the semiconductor industry cope with test challenges faced in the last 15 years. However, these techniques now are reaching a limit in their capability to provide the same level of relief to very deep submicron devices.
Imagine a four million-gate chip with 100,000 flops. With scan, and assuming 16 parallel scan chains, each chain will consist of 6,000 flops. In other words, each test vector will take 6,000 cycles to scan in. This can create a big demand on the time and tester memory for testing such a device.
In addition to the test time, at-speed test of such a device working at 400 to 500 MHz through scan or functional test is a nontrivial task. Such a device will have several tens or hundreds of embedded memories, a couple of predesigned cores, and possibly some analog circuitry such as a phase-locked loop.
The DFT techniques in use for the last 15 years do not provide a well-coordinated, comprehensive, and cost-effective solution for such devices. Another answer is needed.
Fortunately, DFT techniques recently have evolved to a new plateau where critical tester functions are embedded on the chip being tested. The basic idea is to create microtesters for every major functional or architectural block in a chip during design. A network of microtesters can be integrated at the chip level and accessed through the JTAG/1149.1 port to provide a complete test solution. Figures 2 and 3 provide a graphical representation of the conventional vs the embedded test solution.
The embedded test solution moves many back-end test problems to a front-end automated design process. This saves time-to-market and offers designers the ability to verify the first silicon rapidly and conveniently.
There is a fundamental win here: embedded test offers a divide-and-conquer approach to a very complex problem. By removing the need to generate, apply, and collect a large number of test vectors from outside, embedded test reduces the cost of external testers.
The silicon overhead of these microtesters from at least one commercial embedded test supplier is in the range of 1,000 gates each, over and above the scan. As a result, a million-gate chip with 10 of these microtesters only takes 10,000 extra gates; the embedded test total silicon penalty is only 1%.
The embedded test concept is simple to describe, but the technology behind it is sophisticated. Remember, there is no such thing as a free lunch. A simple Linear Feedback Shift Register (LFSR), a basic pattern generator, and Multi-Input Linear Feedback Shift Register (MISR), a basic response compactor, cannot replace the functionality of a million-dollar tester.
An effective solution considers all kinds of issues such as multiple clock domains, clock skews between clock domains, multicycle paths, and tristate buses. Moreover, a comprehensive set of automation tools is needed to make this process an integral part of a chip designer’s environment. Finally, silicon proof from multiple customers is needed to ensure that the whole process actually works as expected.
Research and comprehensive automation tools have created at least one solution that demonstrates the benefits of embedded test on multimillion gate chips. LogicVision’s embedded test has designed chips ranging from hundreds of thousands of gates to multimillion gates.
Table 1 shows two specific examples. Design B had an embedded test silicon penalty of just 1% of the scan design. In fact, as the size and complexity of designs continue to increase, the silicon penalty for embedded test decreases.
Figure 4, a redrawing of Figure 1, illustrates a comparative cost point of view. This figure shows that if the cost of external testers starts to go above unacceptable levels, then embedded test can provide a complementary and effective solution. The embedded test is the new beacon that will guide the semiconductor industry to achieve their time-to-market and profitability goals with the ever-increasing complexity of their products.
About the Author
Dr. Vinod Agarwal is the founder, president, and CEO of LogicVision. From 1978 to 1994, he was on the faculty of the electrical engineering department at McGill University, Montreal, most recently as NT-BNR/NSERC industrial research chair professor. Dr. Agarwal has authored and co-authored more than 100 technical publications and holds several U.S. and Canadian patents. He was elected to the grade of Fellow of the IEEE in 1992. LogicVision, 101 Metro Dr., San Jose, CA 95113, (408) 453-0146, www.logicvision.com.
Size/Complexity
Fault Coverage
Other Benefits
Design A
532,000 logic gates
32 different memories
17 clock domains
22,000 scan flops
100% stuck-at-coverage (64k embedded test vectors and 3k ATPG vectors)
first-pass silicon success
substantial reduction in test time and tester memory
Design B
1 million logic gates
200 different memories
100-MHz clock domains
41,000 scan flops
99.5% stuck-at coverage (no ATPG vectors needed)
97.2% transition fault coverage
embedded tests reused in bring-up and system reuse
design time reduced by months
Copyright 1999 Nelson Publishing Inc.
September 1999
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