Exploring Innovative Flash Test Techniques

One of the key technologies contributing to the record development of mobile communications and consumer mass storage is nonvolatile memory (NVM). Demand for such memory devices, particularly in portable products, seems unlimited due to their unique capability to retain data even when powered off, unlike traditional memory products found in PCs.

The most noticeable growth within the NVM market will be in flash memory for consumer and communications products—primarily digital cameras, MP3 players, personal digital assistants, and wireless communications. These diverse end-use markets will push flash memory performance upwards in terms of density and speed.

Flash memory generally is of two types: NOR and NAND. Named for the architectures they use, each functions differently. NOR flash excels in retrieving a specific piece of data, NAND flash in returning large blocks of data.

A good analogy is a phone book. If a NOR and a NAND device were loaded with identical information from a phone book, the NOR device would produce a specific phone number each time it was accessed. In contrast, a NAND device would produce entire sections of a phone book at once.

In the real world, NOR devices are used in applications such as cellular phones where retrieval of small specific pieces of information is needed. NAND devices, on the other hand, are used in MP3 players and digital cameras that require the transfer of large multimedia files.

Flash memory has been particularly successful because of its nonvolatile nature, low cost per bit, and high functionality. Until recently, however, flash memories have been relatively slow and simple devices. As NVM end-use applications continue to grow and diversify through 2003, flash devices will require more complex synchronous interfaces to fulfill their increasing role in data storage.

Flash-memory performance specifications will need to match those of the devices with which they interface. Test requirements for these devices will raise the maximum operating frequency to 200 MHz, require overall timing accuracy of <±500 ps, and necessitate logic test features, such as deep vector memories, switching between algorithmic pattern generators (APGs), and on-the-fly vector sequencing. These trends are based on data from the International Technology Roadmap for Semiconductors 1999 Edition (Figure 1).

Figure 1. Roadmap of Flash-Memory Test Requirements

Frequency 66 MHz 80 MHz 100 MHz 125 MHz 133 MHz 166 MHz Parallelism 32 64 64 64 64 64 OTA 1 ns 0.75 ns 0.6 ns 0.6 ns 0.5 ns 0.5 ns Vpp Voltage 1.3~13.0 0.6~10.0 0.6~10.0 0.6~10.0 0.6~10.0 0.6~10.0 Vcc Voltage 1.3~5.5 0.6~5.5 0.6~5.5 0.6~5.5 0.6~3.3 0.6~3.3 Data Width 16 32 32 32 32 32 Vector Depth 128k 1M 1M 1M 1M 1M Volume Density 64M 64M 128M 128M 256M 256M Lead Density 256M 512M 512M 1,024M 1,024M 2,048M $/pin $1.15k $1.0k $850 $725 $610 $525 2000 2001 2002 2003 2004 2005

Data-storage-intensive consumer electronic end-market applications are propelling the need for higher-density memory devices and bringing along new developments. NAND density is expected to become 10 times more than that of traditional NOR by 2003 (Figure 2).

All of these flash-technology trends mean one thing: today’s memory testers do not have the performance needed to test the devices that will be available in as little as three years.

Compounding the flash manufacturer’s problem is the continuing price erosion as flash memory becomes more of a commodity product. Although prices have been rising over the last several months because of a supercharged flash market, most analysts project average selling prices of flash devices to trend downward at a rate of approximately 26% per year on a dollars/Mbit basis. As a result, flash vendors will continue to pressure test vendors to lower the cost of test even as the performance and functionality continue to increase.

Flash Testing Techniques

One trend to lower the cost of test (CoT) involves moving at-speed tests to wafer sort. By moving traditionally final test to wafer sort, device manufacturers can reduce the overall cost of test.

CoT can be lowered further through the migration of flash manufacturing to 300-mm wafers, which allows greater parallelism without sacrificing probing efficiency. Because of the asynchronous nature of flash programming and redundancy repair, the opportunity for greater parallelism must be coupled to a tester-per-site architecture, which accommodates independent tester resources for each device under test (DUT) (Figure 3).

The Tester-Per-Site™ architecture is a proven method for testing multiple devices by providing all of the resources of fully independent testers for each DUT. When NVM is tested in a conventional shared-resource test architecture, the slowest memory cell will delay a parallel test operation, and throughput will be reduced. The Tester-Per-Site architecture eliminates this problem.

Increasing parallelism has forced test vendors to push traditional PCB technologies and power-management techniques to the limit to fit more sites and channels into a smaller test head. While several factors are driving up PCB cost, the most significant involves the increasing number of layers being used in multilayer PCBs to meet test-head interconnection needs.

On a conventional PCB, tracks on different layers are connected by plated-through via holes. As designs have become more and more complex, PCB designers have just a few options: reduce the size of tracks and vias, increase the number of layers, and use blind or buried vias.

Because the vias in conventional PCBs are drilled mechanically, the first option is limited by the fact that the smallest practical drill size is about 0.2 mm. However, increasing the number of layers makes the board even more complex, difficult to manufacture, expensive, and less reliable.

Micro-Via Board

One technology to achieve the required system densities is the micro-via board. It contains a multilayer core of high-temperature FR4 board sandwiched between two micro-via layers. The micro-via layers typically consist of a 2.5-mil-thick layer of resin-coated copper with 3-mil-dia laser-drilled micro-vias.

Typically, the smallest features on the board are 3-mil-wide lines with 4-mil spaces. By replacing the conventional drilling operation with a laser-etching process, thousands of micro-via holes can be simultaneously produced without debris generation, drill-bit run-out, drill-bit breakage, or smear.

The Functional Implementation

To meet the challenge of integrating more than 32 sites of 64 channels into a single test head, it is necessary to focus on compact and efficient ASICs.