Toward Optimizing SOC Test

The irrepressible market drive for better, smaller, faster, and cheaper has led to the increasing use of high-end systems on a chip (SOCs) in a host of consumer products in three areas: automotive telematics, the cell phone, and the PDA. This widespread use presents challenges to device manufacturers and test-floor managers as they strive to meet their goals of volume production and economic profitability.

The Devices

In automotive telematics, the 8- and 16-bit generation devices are being relegated to control power windows, heating, and ABS systems. Replacing these devices in the more compute-intensive systems are 32-bit controllers based on RISC and CISC architectures. These new devices are used in a variety of under-the-hood harsh environments such as engine and drive-train control.

A typical engine controller is a 32-bit microcontroller with a 50-MHz CPU core integrated with 1-Mbit flash, 32k SRAM, multiple time processor units, and 10 12-bit analog-to-digital converters (ADCs). Early products in the cell phone/PDA market were built around 16- and 32-bit processor cores. Recent PDA market introductions indicate a trend toward consolidation around RISC cores.

The cell-phone market still is somewhat divided between RISC-based cores and 32-bit cores. These devices combine a 32-bit CPU or RISC processor with a DSP to provide trimode operation across wideband code division multiple access (WCDMA), CDMA, and global system for mobile communications (GSM) bands. The RISC PDA device shown in Figure 1 contains 1 Mbit of flash along with 128k of SRAM. Interfaces to the real world are through 10- and 12-bit ADCs and sensor interfaces for pen and graphic tablet inputs.

In all the examples mentioned here, analog wireless communications, voice processing, and power-management functions are integrated either on the digital chip or in companion analog chips of a chipset. Separating analog devices from digital devices compromises the production mix; integrating analog functions on the digital device complicates the device test requirements.

The Test Problem

The varied production mix means that test-floor managers must provide the flexibility to test analog-heavy devices as well as digital-heavy devices. Existing SOC testers have either multiple dedicated test sets with multiple insertions to test the discrete device functions; expensive, high-end test sets with slow, specialized shared instruments for single-insertion test; or a mix of the two. All three alternatives are expensive, both in test time and capital cost, with an inherently low number of good devices binned per hour.

A simplified test-insertion flow is shown in Figure 2. Probe 1 is the initial functional probe designed to weed out gross failures. This generally is done on a low-cost, lower capability test system. Probe 2 is the memory test and repair step. Due to the depth of memory and complexities of today’s flash arrays, dedicated memory testers often are used with bitmap and redundancy analysis capabilities.

The sizes of the memories in the device shown in Figure 1 imply that memory test and repair would be required to ensure that yield targets are met. After the array has been repaired, the device is packaged and sent to final test. Here the device finally is tested to its full capability, requiring a full set of instrumentation in the SOC tester. Adding further complexity, final test usually is performed under a variety of temperatures.

Inefficiencies are immediately apparent. First, multiple tester types are required. The test floor must maintain multiple test programs, spares kits, an interface, and docking kits, one for each type. Test engineers, technicians, and operators also must be proficient in operating and using each.

Second, multiple device insertions are required. If the functional or SOC tester does not have memory test capability, then at least one insertion on a memory tester is required. Improvements to this situation would be a tester with an efficient memory test capability and high-performance instrumentation for final test but configurable to a low-end, digital-only system to be used at Probe 1.

The third inefficiency is the amount of time spent within each step of the flow. While overall test time depends upon a number of factors (handler/prober index times, uptime, reliability), efficiency of the test equipment itself is a significant factor. Test efficiency is impacted by the density of instruments as well as the capability to perform parallel test. Improvements in these areas would increase both the instrument density and the single-site throughput and support parallel test.

The first inefficiency—multiple tester types—can be addressed by a universal-slot architecture tester. The universal-slot architecture solves the problem by allowing configuration of a common system chassis, software, and the device interface board with different instruments to handle the multiple insertion points.

However, this approach requires an instrument in one slot of the system to be synchronized with the others for proper operation. For example, synchronization would be needed for the SOC device (Figure 1) for starting a pattern on a digital slot and then change a DC meter range on the fly to measure the sleep-mode current drain. This is further complicated because there may be multiple sites, with each site doing the same test but at slightly different times.

Using a distributed, asynchronous pattern generation and timing architecture, as shown in Figure 3, can solve this problem. The distributed architecture is based on a pattern generator and digital synthesizer per board.

The PatGens in the system communicate with each other via a common crosspoint communication hub, allowing instruments from different slots to exchange status, trigger, time-stamp, and pass/fail information. The synthesizer digitally resynthesizes a common master clock for local use. This locally synthesized clock, completely coherent to the system master clock, generates the pattern vectors, digitizer sample rates, or analog waveform source rates as needed by the instrument in that slot. Each analog instrument now can trigger exactly on a vector-by-vector basis.

The second inefficiency—multiple insertions—is addressed by increasing the instrument density. The SOC device in Figure 1 will require a memory test insertion since yield loss in a 1-Mbit flash device probably will be unacceptable without some form of repair. So at a minimum, an efficient memory test option is required.

A universal slot system could be entirely populated with digital instruments and memory test options for the first two wafer-probe steps. This allows the first two steps, Probe 1 and Probe 2, to be combined, eliminating the Probe 1 insertion entirely.

The third inefficiency—lack of parallel test—is impacted by the number of instruments available per site and the efficiency of those instruments. The number of instruments per site affects test-time efficiency by forcing the sharing of resources.

For example, the SOC device in Figure 1 has ADC inputs that require an arbitrary waveform generator (AWG) to provide the required tones. If four devices need to be tested in parallel, then a single AWG would have to test each device sequentially. Having four AWGs would allow each device to be tested independently, with a corresponding 75% test-time benefit.

Impact of Hardware On Software

Two significant developments in SOC test are apparent: embedded memory test capability and extensive pattern control over analog instruments. The system software must provide memory test analysis tools and easy-to-use methods of representing and relating the digital and analog domains. Both also must be optimized for parallel test applications, allowing easy configuration for as many sites as possible.

Two primary memory analysis tools are required for embedded memory test: redundancy analysis and bitmapping. These tools must be incorporated into the SOC tester software.

Redundancy analysis can be performed either off-line or online. If online, it needs to use the distributed pattern generators to efficiently transfer and locally analyze fail data. Once this is done, benefits to memory test time can be dramatic. Preliminary results on the example device in Figure 1 show a 45% improvement for a typical memory test insertion.

A seamless mixed-signal development and debugging environment lowers the expertise required to manipulate the various instruments and speeds device program debug and development by allowing the test engineer to quickly specify relationships among analog and digital pins.

Test Problem Revisited

A universal slot architecture with distributed pattern and clocking means any instrument can appear anywhere in the system, allowing a single platform to be configured to match the requirements of each insertion step. Hardware-efficient memory test with embedded processing coupled with analysis software replaces the dedicated memory tester at Probe 2. This single platform now can be used at each insertion step, greatly reducing the spares count and training requirements.

Advanced technology has allowed instrument density to increase, and with parallel test, there is no need to share instruments between sites. By lowering the digital cost and integrating memory test capability on each digital board, Probe 1 insertion can be eliminated, allowing functional screening at Probe 2.

These improvements help break down the SOC test bottleneck, allowing test-floor managers to meet the twin goals of volume production and profitability.

About the Author

John Whittaker is the applications manager for the Consumer Business Unit at Teradyne. The 15-year veteran of the ATE industry has a background in memory and digital test and statistical analysis software. Mr. Whittaker graduated from Worcester Polytechnic Institute with a B.S.E.E. Teradyne, Consumer Business Unit, 9 Crosby Dr., Bedford, MA 01730, 617-422-2700, e-mail: [email protected]

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July 2002