Slightly out-of-spec DRAMs no longer are doomed to the scrap heap. They can still live useful lives in less demanding applications.
Dynamic random-access memory (DRAM) manufacturers are always developing new generations of chips. Presently, 256-Mb chips and 256-MB dual in-line memory modules (DIMMs) are the most popular memory configurations. As recently as last summer, it was the 128-Mb and the 128-MB that gained favor.
DRAM-Wafer First-Pass Test
The first-pass test on a DRAM wafer is performed on ATE, a relatively large system made especially for detailed test of memories. This machine usually comes with a measurement head for DC parametric tests. The measurement head has the capability to measure DC current as low as 10 µA.
Due to the imperfection of the process, a percentage of the DRAM die contains some faulty cells. Manufacturers improve their yield by applying a laser repair process that cuts away the known-bad memory cells and replaces them with spare cells on the same die.
To isolate the bad cells, manufacturers must excite the entire memory array on the chip. That means every cell on the chip has to be exercised and tested. The test performed normally is called the functional test.
Selected test patterns are written into each cell and read back in a special sequence to verify proper functionality. To reduce the test time, parallel chip testing usually is accomplished with eight to 16 chips in a row.
This test is performed at the wafer level with automatic die stepping probes. A special ink jet color marks the good dies. The wafer then is sent for laser repair and to the backend for die separation and final packaging. Functional test is performed again at the post-package level.
Inked Die Don’t Always Make It All the Way Through
A chip manufacturer is concerned with contaminants that initially would hide problems during the processing operations. Burn-in test usually weeds out this infant-mortality problem. Live burn-in is done with the chips in a chamber at elevated temperature, usually 50°C to 70°C for 72 hours. To save time, an elevated supply voltage is applied to accelerate the aging process. During the test, signals are applied to the DRAMs to keep them in the active state.
Depending on the maturity of the process and the design, some percentage of chips usually fails the manufacturer’s specifications during the functional test following burn-in. They either have bad cells or simply do not pass a certain pattern test.
Since these chips already are in the final epoxy package, the DRAM manufacturers sell them as downgrade or C-grade chips. To protect the DRAM manufacturer, these downgrade transactions usually are sold with an agreement that the buyer not expose the origin of the chips.
Downgrade Memory-Module Manufacturers
There is a class of memory-module manufacturers commonly known as downgrade manufacturers. Rather than use DRAMs from the regular channel, these manufacturers buy C-grade DRAMs from regular memory-chip manufacturers and produce what generally are termed OEM memory modules.
Since these chips are known-bad chips, they first must go through stringent tests and be separated into different failure classifications. According to the classification and the test result, these chips are assembled onto specially designed DIMM PCBs that can turn partially bad chips into a working memory module.
How Downgrade Chips Are Sorted
C-grade memory chips can be tested and classified into the following categories:
- All bits functional.
- Partially good with address line fault.
- Partially good with data line fault.
- Not functional.
The objective is to find out which bits are good and usable. For example, a 32-Mb × 8 chip might only have 4 bits bad; the remaining 4 bits are usable. As a result, these chips still can be made into a good memory module using 16 chips instead of the regular eight chips.
To make the classification simple, the good bits in a × 8 downgrade DRAM are indicated by A, B, C, and D (Figure 1). A represents D0 and D1 (data line #0 and data line #1), B for D2 and D3, C for D4 and D5, and D for D6 and D7. If a × 8 DRAM has D0 to D3 as good bits, the chip would be classified as an AB. Likewise, a DRAM chip with D4 to D7 good would be classified as a CD. There are 11 combinations:
Four bits good: AB, AC, AD, BC, BD, CD
Six bits good: ABC, ABD, ACD
Eight bits good: ABCD
Eight bits bad: Blank
Equipment Used for Downgrade Testing
Downgrade memory-chip sorting usually is done in third-world countries where labor costs are low. This is due to the long and tedious categorization that requires human intervention. The process also is performed on very low-cost equipment.
First, there is a chip carrier that looks like a DIMM. Instead of soldered-down TSOP package DRAM chips, the carrier has TSOP test sockets. Eight chips can be plugged into the eight sockets. The entire chip-carrier module then is tested as if it were a DIMM. The test can be performed on a motherboard or a low-cost memory-module tester.
The downgrade test motherboard is no different from a regular CPU board. However, the software is quite different. This custom software usually resides in the system BIOS to provide direct control of the memory port and directly distinguishes the combination of bit failures.
The advantage is the capability to test two carrier modules with eight chips each at the same time. However, the test takes more than 10 minutes to complete. Also, the BIOS software normally is quite expensive and becomes obsolete with each generation of motherboard.
Another way to test these chips uses a low-cost DIMM tester. These testers normally are made to test regular DIMMs. With minimal modification to the test software, the tester can display the good bits in A, B, C, and D. These testers are fast and feature a simple user interface. They also are low cost and compatible with many generations and configurations of chips.
Classify by Bad Address
When the most significant address line fails on a DRAM chip, it translates into no-access on half of the memory cells. However, the other half of the cells still can be used functionally. For that reason, these single-address failed chips are classified in two categories:
Stuck High—the upper half of the DRAM cells is good.
Stuck Low— the lower half of the DRAM cells is good.
Using Downgrade DRAM in Memory Modules
The ABCD classification chips usually are good enough to be assembled as regular DIMMs. Although they failed the original manufacturer’s tests at one time, they are just slightly out of spec and usually used in a lightly loaded system. These modules usually are marked and sold as OEM-grade DIMMs.
The four-bits good (example: AB) and the six-bits good chips (example: ABC) are used with a specially designed DIMM PCB. In the case of the four-bits good chip, the PCB emulates an eight-bits good chip by putting two four-bits good chips back to back (Figure 2). Overall, there are nine types of special design DIMM PCBs to accommodate all combinations of partially good chips.
For the high and low categories, the DIMM would be more complicated. A special ASIC chip must be used to combine the column address lines on two chips and reconstruct the complete set of good address lines. These ASIC chips are available from small vendors in Taiwan. Two types of PCBs are designed to use this kind of chip. One design covers the high-address chips, and the other one accommodates the low-address chips.
What Happens to the Not-Functional Chips?
The many DRAMs that do not pass the downgrade test for memory modules are not completely scrap. These chips usually are sold as sweeps, from the phrase sweeping the floor. They still might have some good bits that can be used in audio applications.
A digital answering machine is a purely digital audio application. Users usually don’t notice a few pops during operation. The sorting specification is no more than one bad bit within every 16 bits. One small block of completely good cells also is needed in the first quadrant to host the operating system.
Since DRAM cells usually fail in a cluster confined to a small area, consecutive bad cells can be redistributed through address scrambling. This method calls for reconnecting address lines in a different sequence to disburse the bad cells into nonconsecutive locations.
These applications require custom sorting of DRAM chips. The sorting is performed according to specific application needs. High-volume usage usually is the criterion to justify this kind of custom sorting with specially designed testing software.
About the Author
Cecil Ho is the CEO of CST. Before founding the company in 1983, he spent more than 14 years as a design/program manager with Texas Instruments and General Instruments. Mr. Ho holds a membership in Who’s Who in the Electronic Industry; Eta Kappa Nu, an electrical engineering honor society; the JEDEC Committee setting memory standards; and AMII, participating in the enablement of next-generation memories. He has a B.S.E.E. with postgraduate credits from the University of Texas. CST, 2336 Lu Field Rd., Dallas, TX 75229, 972-241-2662, e-mail: [email protected]
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March 2003