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Divide and Conquer: Hierarchical DFT for SoC Designs
May 24, 2016
Mentor Graphics
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![WhitePaper_UPDATE[1]](https://img.electronicdesign.com/files/base/ebm/electronicdesign/image/2016/05/WhitePaper_UPDATE1.png?auto=format,compress&fit=&q=45&h=139&height=139&w=250&width=250 "WhitePaper_UPDATE[1]")