Having hardware that can be programmed after manufacturing is key for factory cameras that identify rotten food on an assembly line, wireless base stations that process cellular signals or corporate servers crunching machine learning tasks. It would be too costly to retool these applications with new chips every couple of years, so companies install field-programmable gate arrays – more commonly known as FPGAs.
That was the reasoning behind Intel’s $16.7 billion acquisition of Altera, one of the world’s largest makers of the chips. But the Santa Clara, California-based company is also betting on customers outgrowing its programmable silicon. Once no more changes are required, many companies convert an FPGA into an application-specific integrated circuit, or ASIC, which is severely less programmable but much more power efficient.
On Monday, the company announced that it would buy Santa Clara, California-based eASIC, which has developed an alternative to standard ASICs for embedded applications and data centers . The company, which employs around 120 people and is led by chief executive Ronnie Vasishta, works with customers to convert FPGAs into custom chips faster and cheaper than regular ASICs.
“You take an FPGA to market and in certain areas when the design stops changing and you have extremely high volumes, you think about going with an ASIC,” said Dan McNamara, vice president and general manager of Intel’s programmable solutions group, adding that the deal would let it hold onto customers that decide to convert. “We really think customers will see value in partnering with us for the entire lifecycle,” he told Electronic Design.
Intel declined to disclose the financial terms of the deal, which will likely close in the third quarter. The acquisition is targeted at filling the holes that have formed in Intel’s business as production costs rise and rivals close the gap on its manufacturing lead. eASIC could also help protect Intel’s lead in data centers, where the center of gravity is shifting from processors to accelerators, which include GPUs and FPGAs as well as ASICs.
Intel plans to integrate eASIC, which was valued at $110 million last year, with its programmable solutions group. The group has blossomed as cloud computing companies like Microsoft use its chips as server accelerators. In the first quarter, the business unit said revenues rose almost 20 percent to $498 million and server sales jumped 150 percent over the last year. The division also sells chips for industrial, medical, automotive and other applications.
Intel is trying to maintain its data center dominance by pairing server chips with FPGAs, which contain separate routing and logic blocks arranged in a checkerboard pattern. The connections inside the chip can be programmed to implement any desired function. But to support that level of programmability, the chips are typically expensive and bulky. The connections are hardwired into ASICs, shrinking the die space while boosting efficiency.
Designing ASICs is normally expensive because every device requires a new batch of masks, basically the blueprints for the manufacturing process. eASIC has developed what are called structured ASICs, which only require one or two masks. The chips strike a balance between the performance of ASICs and the development costs of FPGAs. The technology once competed with Altera’s discontinued ASIC product line, Hard Copy.
McNamara told Electronic Design that eASIC accelerators can be designed in three to five months, around five times faster than traditional ASICs, which can save customers up to millions of dollars in developments costs. Currently, customers can convert both Intel and Xilinx FPGAs into 28-nanometer devices. Intel is also considering whether to take over eASIC’s production from GlobalFoundries and Taiwan Semiconductor Manufacturing Corporation.
The technology also feeds into Intel’s machine learning strategy. Increasingly, Intel’s FPGAs are used to run inference tasks in data centers, where training is usually handled by Nvidia’s graphics chips. They can be updated to conform to machine learning algorithms, which are still evolving. In contrast, custom ASICs must be redesigned to accommodate new algorithm advances, and that can be prohibitively expensive. eASIC offers a compromise.
“Ultimately, there will come a point where things will settle out and you will want to reduce the cost and power of FPGAs,” said McNamara, previously vice president of Altera’s embedded division. “Graphics chips and neural network processors will be there, but eASIC gives us another destination for FPGAs once things settle out.” He added: “We’re going at machine learning with a full portfolio depending on what the customer is trying to solve.”
Since it was founded in 1999, the company has raised $140 million from investors including Kleiner Perkins Caufield & Byers and Khosla Ventures. eASIC’s customers include Huawei, Seagate and Flir Systems. “For us, it’s about adding investment that allows them to scale more quickly, and get them a much broader sales and marketing team to get out there,” McNamara said. “They have really good technology, it’s just about getting it out there.”
