DDR Debug Toolkit provides test, debug, and analysis

Dec. 1, 2014

Teledyne LeCroy has introduced the DDR Debug Toolkit for complete physical layer analysis of DDR 2/3/4 and LPDDR2/3 signals. Most oscilloscope-based DDR physical layer test tools on the market are targeted exclusively at JEDEC compliance testing, whereas the DDR Debug Toolkit provides test, debug, and analysis tools for the entire DDR design cycle.

With a push of a button, read and write bursts can be separated and eye diagrams for each can be displayed in real time, quickly providing insight to system performance. Users can identify the root cause of problems with jitter analysis specifically designed for the bursted DDR signals that conventional serial data tools cannot analyze. A variety of DDR-specific measurement parameters are built in to the toolkit enabling an easy quantitative analysis of system performance. All this DDR analysis can be performed simultaneously over four different measurement scenarios allowing for a deep understanding of system performance, improving DDR testing efficiency, and providing faster results.

The ability to display up to ten eye diagrams simultaneously provides a high-level view of system performance during system bring-up. The multi-measurement scenario analysis capability easily lends itself to optimization and tuning of system and device performance, while the built-in measurements provide characterization benchmarks for pre-compliance testing. For those testing to the JEDEC standards, the analysis tools can be leveraged to perform margin testing and to troubleshoot any failures which arise during compliance testing. Additionally, the DDR Debug Toolkit provides an alternative to automated DDR compliance test packages for times when full compliance testing is not required.

Teledyne LeCroy offers a complete range of DDR test solutions covering physical layer validation and debug to protocol test. QualiPHY automated compliance framework provides automated physical layer testing for DDR2/3/4 and LPDDR2/3, and the DDR Debug Toolkit offers insight at every step in the DDR design cycle. The Kibra line of protocol analyzers is the first standalone protocol analyzer for DDR supporting both DDR3 and DDR4. It offers compliance analysis as well as full protocol and performance analysis.

Immediately available, the DDR Debug Toolkit starts at $3,000 and is available for WaveRunner 6 Zi, WavePro 7Zi-A, WaveMaster 8Zi-A, LabMaster 9Zi-A, and LabMaster 10 Zi platforms.

teledynelecroy.com

About the Author

Rick Nelson | Contributing Editor

Rick is currently Contributing Technical Editor. He was Executive Editor for EE in 2011-2018. Previously he served on several publications, including EDN and Vision Systems Design, and has received awards for signed editorials from the American Society of Business Publication Editors. He began as a design engineer at General Electric and Litton Industries and earned a BSEE degree from Penn State.

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