DesignCon 2019 names Engineer of the Year winner, announces 2019 Best Paper Award finalists

“The finalist judges were extremely impressed with the quality of entries we received this year for the Engineer of the Year Award. Vishram Pandit’s dedication for advancing the industry rose above the rest in our open voting. Specifically, impressive was his instrumental role in the development of new PI/SI methodologies that significantly changed how the industry operates,” said Naomi Price, conference content director, UBM. “Pandit’s contributions to the field of engineering have been nothing short of remarkable and it is a privilege to grant him this well-deserved recognition.”

“I’m deeply honored to receive the Engineer of the Year award from such a well-respected institution and also to get the opportunity to contribute to the communities that supported me along my engineering path,” said Pandit.

About Vishram Pandit
Pandit currently serves as a SoC Platform Architect at Intel where he brings his 20+ years of experience in electronic engineering to focus on finding ways to improve and co-optimize system power delivery spanning PCB, Package, and Chip. At Intel, Pandit leads and provides technical guidance on developing various new PI/SI methodologies that support spec development, optimization, area savings, Platform BOM cost reduction, and product quality improvement.

Pandit has been a key contributor to methodologies in on-chip power integrity, system-level power integrity impact, and signal/power integrity co-design, successfully deploying them on various Intel products. During his tenure at Intel, Vishram has received various awards for his technical contributions and became co-author of a book, “Power Integrity for I/O Interfaces: with Signal Integrity/Power Integrity co-design” in addition to being co-author of approximately 30 conference and journal publications.

Pandit is an active member of the DesignCon Technical Program Committee and serves as a co-chair for Track 11, covering power integrity in power distribution networks. 

This year at DesignCon, Pandit presented the technical session, “Electrical Integrity for LPDDR5 Memory Technology.”

About DesignCon Best Paper Awards
DesignCon Best Paper Awards recognize outstanding contributions to the educational goals of the DesignCon program. DesignCon Best Paper Award recipients are selected through a two-prong process. The first step is a review of the full-length papers accepted for the current year's program. Members of the DesignCon Technical Program Committee rank these papers based on quality, relevance, impact, originality, and lack of commercial content, which determines the finalists. While selection as a finalist for a DesignCon Paper Award is a notable achievement in itself, winners are then chosen from the finalists based on the quality of their presentations. Presentation quality is judged based on audience feedback collected at DesignCon.

2019 BEST PAPER AWARD FINALISTS

• Simulation & Measurement Correlation of Power Supply Noise Induced Jitter for Core & Digital IP Blocks
  Hyo-Soon Kang, Intel Corporation; Guang Chen, Intel Corporation; Ashkan Hashemi, Intel Corporation; Wern Shin Choo, Intel Corporation; David Greenhill, Intel Corporation; Wendem Beyene, Intel Corporation
• Top-Down Jitter Specification Approach for HBM System Optimization
  Hing “Thomas” To, Xilinx Inc.; Nanju Na, Xilinx Inc.; Anna Wong, Xilinx Inc.; Haixin Ke, Xilinx Inc.; Ajay Kumar Sharma, Xilinx Inc.; Wui Hung Moo, Xilinx Inc.
• A Review of Combiner/Divider PCB Design Topologies for 5G & WiGig ATE Applications
  Giovani Bianchi, AdvantestJosé Moreira, AdvantestAlexander Quint, Kalrsruhe Institute für Technologie
• On the Minimization of PCB Differential Pair Skew or Its Effect
  Syed. A. Bokhari, Fidus Systems Inc.
• PCB Interconnect Modeling Demystified
  Lambert (Bert) Simonovich, Lamsim Enterprises Inc.
• 6.4Gb/s Single-Ended Transceiver Techniques for DDR5 Server Application
  Tingting Pang, Huawei Technologies; Tianyu Liang, Huawei Technologies; Zhihua Xu, Huawei Technologies
• A Methodology for Performance Comparison of Center & Edge Sampling in Serial Links
  Hossein Shakiba, Huawei Canada – HiLink; Shayan Shahramian, Huawei Canada – HiLink; Behzad Dehlaghi, Huawei Canada – HiLink; David Cassan, Huawei Canada – HiLink; Davide Tonietto, Huawei Canada – HiLink
• Partitioning of TX & RX Feedforward Equalizer for 112-Gbps Serial Links
  Kevin Zheng, Xilinx Inc.; Boris Murmann, Stanford University; Hongtao Zhang, Xilinx Inc.; Geoff Zhang, Xilinx Inc.
• Baseline Wander: Systematic Approach to Rapid Simulation & Measurement
  Pavel Zivny, Tektronix; Vladimir Dmitriev-Zdorov, Mentor, a Siemens Business; Maria Agoston, Tektronix
• 100+ Gb/s Ethernet Forward Error Correction (FEC) Analysis
  Cathy Ye Liu, Broadcom Inc.
• A Fast & Simple RFI Mitigation Method without Compromising Signal Integrity
  Qiaolei Huang, Missouri University of Science and Technology; Ling Zhang, Missouri University of Science and Technology; Yang Zhong, Missouri University of Science and Technology; Jagan Rajagopalan, Amazon Lab126; Deepak Pai, Amazon Lab126; Chen Chen, Amazon Lab126; Amit Gaikwad, Amazon Lab126; Chulsoon Hwang, Missouri University of Science and Technology; Jun Fan, Missouri University of Science and Technology
• Using Multiple Huygens Boxes to Detect & Quantify the Coupling Path from Noise Source to Victim
  Antonio Ciccomancini Scogna, Futurewei Technologies Inc.;Jiangqi He, Futurewei Technologies Inc.;Cheng Wei Chang, Huawei; Liu Chen Jun, Huawei
• DFE Implementation & Optimization Considerations for Test & Measurement
  Kalev Sepp, Signal Integrity Consultant for VESA, Sepson Analytics LLC
• How the Braid Impedance of Instrumentation Cables Impact PI & SI Measurements
  Istvan Novak, Samtec; Jim Nadolny, Samtec; Gary Biddle, Samtec; Ethan Koether, Oracle
• Demistifying Edge Launch Connectors
  Raul Stavoli, Carlisle IT; Davi Correia, Carlisle IT; Emad Soubh, Carlisle IT
• Effect of PCB Fabrication Variations on Interconnect Loss, Delay, Impedance & Identified Material Models for 56-Gbps Interconnect Designs
  Alex Manukovsky, Intel; Yuriy Shlepnev, Simberian
• Thermal & SI/PI Co-Analysis to Quantify PCB Signal Loss Due to Temperature Variation
  Hongfei Yan, Intel; Xiaoning Ye, Intel; Yinglei Ren, Intel; Chunfei Ye, Intel
• Accelerating 56G PAM4 Link Equalization Optimization Using Machine Learning-based Analysis
  Ting Zhu, Hewlett Packard Enterprise; Yongjin Choi, Hewlett Packard Enterprise; Jacky Chang, Hewlett Packard Enterprise; Chris Cheng, Hewlett Packard Enterprise

DesignCon 2019 is also supported by The Institute of Electrical and Electronics Engineers (IEEE), offering its accreditation to conference attendees. Each conference hour is equivalent to one professional development hour (PDH), and 10 PDH’s result in one continuing education unit (CEU) and an official IEEE certificate. IEEE accreditation can be used to meet training requirements, stand out to future employers, and maintain an engineering license.

About DesignCon
DesignCon is the world's premier conference for chip, board, and systems design engineers in the high-speed communications and semiconductor communities. DesignCon, created by engineers for engineers, takes place annually in Silicon Valley and remains the largest gathering of chip, board and systems designers in the country. This three-day technical conference and two-day expo combines technical paper sessions, tutorials, industry panels, product demos and exhibits from the industry's leading experts and solutions providers. More information is available at: www.designcon.com. DesignCon is organized by is organized by UBM, which in June 2018 combined with Informa PLC to become a leading B2B information services group and the largest B2B Events organizer in the world. To learn more and for the latest news and information, visit www.ubm.com and www.informa.com.