Lattice Semiconductor’s CertusPro-NX pushes the high end of the Nexus product line (Fig. 1). It’s built on the Nexus FDSOI transistor technology that provides high performance with low-power requirements. Competing products use up to 4X the amount of power for the same performance as the new family. The chips come in packages as small as 9 × 9 mm.
Up to 100K logic cells fit into these chip packages, along with SERDES that run at speeds up to 10.3 Gb/s/lane (Fig. 2). Thanks to the multiprotocol physical coding sublayer (PCS), the chips can handle protocols like PCI Express (PCIe) Gen 3 and 10 G Ethernet.
The FPGAs feature large and small internal memory blocks designed for low-latency operation. The chips also support LPDDR4 external memory. Large amounts of on-chip memory are included to meet the changing needs of designers. Likewise, the DSP support has been enhanced to work with machine-learning (ML) applications.
Lattice targets rugged and safety-critical applications with these FPGAs—the chips have an operating temperature range from −40 to 125°C. Their soft error rate is significantly better than the competition. The smallest package limits the number of SERDES and I/O but not the number of logic cells (Fig. 3).
Software support for the CertusPro-NX includes the new Radiant 3.0 development tool. SERDES analysis has been enhanced so that the chip can handle the higher-bandwidth SERDES. Other enhancements in this new version include better signal traceability throughout the design flow, with graphical feedback showing signal traces between the HDL source and RTL view.
This version of Radiant supports two synthesis engines: the Lattice Synthesis Engine (LSE) and the Synplify Pro synthesis engine. The same timing constraints and timing analysis are utilized by both. Timing analysis now runs independently of other operations, providing significant speed benefits and improving an iterative design process—changes need only run timing analysis, mapping, and place-and-route when required. Overall, new Radiant 3.0 features reduce runtime by 15% while delivering a 7% increase in design performance.
