Dual-Series MCUs Address Automotive Safety-Critical Apps Up to ASIL D

What you'll learn:

• What are the main automotive design challenges addressed by each of the new MCU series?
• The level of security provided by the MCUs.
• What is phase-change memory, which is incorporated in both the Stellar G and P MCUs?
  

The complexity of new car architectures requires automotive microcontrollers to deliver higher capabilities. These demanding applications are pushing the limits of MCU architectures due to their need for more processing power, lower power consumption, and larger memory sizes.

To meet this demand, STMicroelectronics has started delivering the first Stellar series of automotive microcontrollers. It’s said that they’re particularly suited to domain and zone controllers to help simplify vehicle wiring, and enable migration to software-defined platforms.

The MCUs combine two series, based on the same architecture, tailored to their application domains. The Stellar P series is designed to meet the demands of integrating the next generation of drivetrains, electrification solutions, and domain-oriented systems. The Stellar G series addresses the key challenges of body integration and zone-oriented vehicle architectures.  These MCUs can host multiple applications, including virtualization of safety and security.

ST is supplying the first devices to new car projects scheduled for production. “These MCUs are critical enablers for tomorrow’s smart, connected vehicles that aim to be safer, more sustainable, and deliver more rewarding user experiences while allowing car makers and their selected partners to strengthen customer relationships with value-added services,” said Marco Monti, President, Automotive and Discrete Group, STMicroelectronics.

Stellar G Series

Addressing body integration and zone-oriented vehicle architectures, the Stellar G series features low-power modes supporting low quiescent current and an intelligent monitoring subsystem. The Stellar G Integration MCUs—SR6G7C3 and SR6G7C7—feature accelerators for secure data routing via CAN, LIN, and Ethernet networks, and they deliver a large set of communication interfaces including 100/1000-Mb/s Ethernet, CAN-FD, LIN, as well as external memory interfaces such as Hyperbus/OctalSPI and eMMC interfaces. 

Embedding a non-volatile phase-change memory (PCM) of up to 20 MB, Stellar G and Stellar P Integration MCUs deliver fast read access times and single-bit alterability (not available in flash memory) that prevents single-bit failures and opens new ways for applications and software to use memories between non-volatile memory (NVM) and RAM storage. Embedded PCM (ePCM) is a back-end technology that separates the non-volatile memory-cell process module from the complex logic-transistor modules in the front end. As a back-end, metallization-based process, ePCM is technology-independent, so it can be embedded in virtually any technology node.

Stellar G MCUs feature up to six Arm Cortex-R52 cores. Some operate in lockstep and some in split-lock mode to fulfill different application needs in terms of safety levels and processing capability.

Stellar P Series

Stellar P MCUs—the SR6P7C3 and SR6P7C7—deliver high real-time and deterministic processing capabilities and feature up to six Arm Cortex-R52 cores, too. Stellar P microcontrollers offer timed IO capability (including GTM4 timers), fast analog capability with embedded signal processing, dedicated sensor/actuator interfaces, and high-temperature support (up to a junction temperature of 165°C) for next-generation drivetrain and electrification systems.

Stellar MCUs leverage the company’s 28-nm fully depleted silicon-on-insulator (FD-SOI) process technology, which has soft-error-rate (SER) immunity to ensure high system reliability and availability for ISO 26262 functional-safety applications up to ASIL-D. FD-SOI s a planar process technology that delivers the benefits of reduced silicon geometries while simplifying manufacturing. Combining 28-nm FD-SOI and PCM enables memory array sizes that are 4X to 5X larger than what’s achievable with flash on bulk 40-nm CMOS.

Virtualization

Stellar Integration MCUs introduce features that include hardware support for virtualization, allowing multiple software applications to coexist safely. It also enhances flexibility for designers by allowing multiple independent applications or virtual electronic control units (ECUs) in the same physical MCU.

A software separation platform for application integration enables embedded virtualization through Cortex-R52 hypervisor privilege level, hypervisor, and application Virtual Machine ID (VMID) based resource access protection at all levels of the architecture (mainly core MPUs and network-on-chip firewalls).

Security Measures

Moreover, Stellar MCUs offer security capabilities for encrypted and safe communication over Ethernet or CAN with an embedded hardware security module (HSM) and dedicated AES-light cryptographic accelerators able to run ASIL D cryptographic functions.

The HSM has full support for EVITA (E-safety Vehicle Intrusion Protected Applications) cyber-protection architecture combined with multi-bus routing to protect connectivity to time-sensitive vehicle networks (Ethernet, CAN-FD, LIN). The HSM is extended with cryptographic engines in lockstep to support secure ASIL D functionalities. In addition, it provides high-speed security cryptographic services and safe network authentication to further protect manufacturer firmware as well as end-user data. 

The MCUs also offer dedicated encryption accelerators for MACsec (Media Access Control security protocol), IPsec (IP security protocol suite), and CAN authentication.

Phase-Change Memory

One of the most challenging demands for larger embedded memories is to hold bigger and more complex firmware. The Stellar Integration MCUs’ non-volatile PCM provides fast read access times, single-bit overwrite capability that’s not available in flash memory, and over-the-air (OTA) updates with no downtime even for full-sized memory updates.

With single-bit alterability, PCM technology delivers better write and comparable read performance than flash-based memories that require at least a byte or a sector-erase cycle before reprogramming. Such single-bit alterability simplifies software handling of data storage. ST’s implementation supports high-temperature data retention, including during solder reflow, so that firmware can be uploaded to PCMs before mounting and soldering.

The first Stellar P and G series MCUs have up to 20 MB of PCM, which ensures high performance and data retention and is compliant with AEC-Q100 Grade 0. The fundamental mechanism for PCM was invented in the 1960s by Stanford Robert Ovshinsky. ST holds a license to the patents resulting from that original development and has built on that work for more than 15 years, developing the ePCM solution that’s integrated into its 28-nm FD-SOI technology platform.

PCM is created using a germanium-antimony-tellurium (GST) alloy. It takes advantage of rapid heat-controlled changes in the material’s physical property between amorphous and crystalline states. These states, which correspond to logic 0 and 1, are electrically differentiated by high resistance in the amorphous state (logic 0) and low resistance in the crystalline state (logic 1).

With the ability to read and write at low voltage, PCM offers several substantial advantages over flash and other embedded memory technologies. PCM access time also is faster than other non-volatile memories such as 1T (single transistor) NOR flash.

The integration of conventional floating-gate embedded NVM (eNVM) represents a significant technical challenge at 28 nm and smaller silicon geometries in both FD-SOI and FinFET CMOS technologies. New NVM technologies, based on the functional properties of particular exotic materials, employ radically different physical mechanisms than those used with flash memory and provide a more effective solution to the process integration difficulties raised by 28-nm CMOS.

AEC-Q100 Qualified

In addition to a rich feature set, Stellar MCUs have routing capabilities that address the architectural evolution with domain and zone controllers and meet the high bandwidth requirements of tomorrow’s vehicles. According to ST, its ePCM technology has been developed and tested to meet automotive requirements for AEC-Q100 Grade 0 with an operating junction temperature up to +165°C. This assures firmware/data retention through high-temperature soldering reflow processes for additional data safety. It also features radiation hardening.

Finally, the speed/power characteristics of the ePCM macrocell and its roadmap at smaller geometries offer a scalable solution for large embedded memories as well as provide enhanced flexibility for designers by allowing multiple independent applications or virtual ECUs in the same physical MCU.