This video is part of our electronica 2022 coverage and the TechXchange: Automotive Radar
The RASIC CTRX family of radar MMICs from Infineon consists of 76- to 81-GHz devices based on 28-nm CMOS technology. The improved signal-to-noise ratio and linearity of the transceiver provides high system-level performance and resilience. The RASIC easy-to-use CTRX8181 transceiver, the first product in the series, simultaneously offers a scalable platform approach for different sensors including corner, front, and short range, along with flexibility for new software-defined-vehicle architectures.
The CTRX8181, developed according to the latest ISO26262 safety standards, comes with four transmit and four receive channels. The higher RF-channel count with improved linearity also enables 33% higher vertical or angular resolution. The in-chip digital phase-locked loop (PLL) accelerates ramps for better range resolution and ultra-fast flyback times. This new feature reduces power consumption and enables more accurate speed information. In addition, it allows for a completely free, configurable ramp without compromising phase noise, making the radar robust and reliable in different scenarios.
The new CTRX product family is best combined with Infineon's radar-specific AURIX MCUs TC3x and upcoming TC4x, both with integrated signal processing units (SPUs) and non-volatile memory for on-chip program code storage. The AURIX chipset and CTRX help deliver the best performance for future NCAP and real-world scenarios, such as improved reliability for radar function in bad weather conditions.
The system partitioning gives vendors the flexibility to offer traditional solutions with full processing capabilities in the radar. However, it also allows for different architectures such as pre-processed data streaming over 100-Mb/s or 1-Gb/s Ethernet with minimal effort. Furthermore, the splitting makes possible the selection of appropriate MMICs and microcontrollers for target applications to facilitate easy scaling with regard to supporting various cost and performance requirements. The connection to the MCU is established via either LVDS or CSI-2.
Related links:
