Mobile Systems Get Performance Boost From Next-Gen ARM Core

Nov. 7, 2005

Based on the next-generation ARM v7 architecture, ARM's Cortex-A8 processor delivers up to 2000 Dhrystone MIPS (DMIPS). It's optimized for low-power next-generation mobile devices. The dual-issue superscalar core includes the first implementation

Dave Bursky

Based on the next-generation ARM v7 architecture, ARM's Cortex-A8 processor delivers up to 2000 Dhrystone MIPS (DMIPS). It's optimized for low-power next-generation mobile devices.

The dual-issue superscalar core includes the first implementation of ARM's NEON signal processing extensions as well as Thumb2 technology for better code density, improved energy efficiency, and higher performance (see the figure). This combination makes the core a good match for consumer products running multichannel video, audio, and gaming applications.

The Cortex-A8 runs at more than 600 MHz in low-power 65-nm processes. The core consumes less than 300 mW and uses less than 4 mm² of silicon (excluding NEON, Trace technology, and L2 cache). High-performance consumer designs will be able to run the Cortex-A8 at up to 1 GHz in high-performance 90- and 65-nm processes (2 DMIPS/MHz). The single-instruction/multiple-data NEON engine includes its own floating-point unit and leverages shared access to the L1 and L2 caches.

New ARM Artisan cell libraries enable the processor's high speed and power efficiency. These libraries also support Intelligent Energy Manager (IEM) technology and implement advanced leakage control structures. Designers used a combination of synthesized and handcrafted cells as well as the just-released poweraware AdvantageCE cell library. Even the caches employ power-smart technology to minimize active power drain. The L2 cache can support memory sizes from 64 kbytes to 2 Mbytes, while the L1 data and instruction caches are 32 kbytes each.

A wide range of ARM technologies supports the processor for rapid system design, including RealView Developer software development tools; RealView Architect ESL tools and models; Core-Sight debug and trace technology; and software library support through the OpenMAX multimedia processing standard. The powerful NEON signal processing extensions can accelerate algorithms for media codecs like H.264 and MP3.

The Cortex-A8 core also includes ARM's Jazelle-RCT (runtime compilation target) Java acceleration technology to optimize Just In Time (JIT) and Dynamic Adaptive Compilation (DAC) (see "Java Gets New Shot In The ARM," p. 66). The RCT scheme reduces the memory footprint by up to three times. Additionally, the processor features TrustZone technology for secure transactions and digital rights management (DRM).

Contact ARM for licensing terms.

ARM Ltd.
www.arm.com

About the Author

Dave Bursky | Technologist

Dave Bursky, the founder of New Ideas in Communications, a publication website featuring the blog column Chipnastics – the Art and Science of Chip Design. He is also president of PRN Engineering, a technical writing and market consulting company. Prior to these organizations, he spent about a dozen years as a contributing editor to Chip Design magazine. Concurrent with Chip Design, he was also the technical editorial manager at Maxim Integrated Products, and prior to Maxim, Dave spent over 35 years working as an engineer for the U.S. Army Electronics Command and an editor with Electronic Design Magazine.