The Fundamentals Of Integrating USB 3.0 IP On An SoC

Early adoption of USB 3.0 began in 2010, and more than 70 million USB 3.0 host chips shipped in 2011. Now, key USB software and systems providers are shipping high volumes of products with USB 3.0. The USB 3.0 ecosystem is in place. USB 3.0 is no longer just for cutting-edge applications. The time has come for all system-on-a-chip (SoC) designers to implement USB 3.0. Are you ready?

This article will help you prepare for the technical challenges associated with integrating a compliant USB 3.0 solution. You’ll understand implementation considerations in using USB 3.0 IP, including selecting configurable controller intellectual property (IP) and robust physical-layer (PHY) IP. Finally, we’ll get into the challenges and solutions for IP testability, verification, hardware validation, driver implementation, and interoperability testing.

Key Features Of The USB 3.0 Protocol

Two primary enhancements defined in the USB 3.0 protocol address the PC and mobile market demands for higher performance and energy efficiency: adding a second physical datapath and replacing continuous polling with an interrupt-driven protocol. Understanding these enhancements helps developers appreciate the technical challenges behind building USB 3.0 IP and focus on the key requirements for selecting ideal third-party IP for their applications.

Second Physical Datapath

USB 3.0 supports 5-Gbit/s performance, which is 10 times the performance of USB 2.0’s 480-Mbit/s throughput. USB 3.0 technology achieves this performance by adding a second physical datapath that operates in parallel with a USB 2.0 data bus. At a PHY level, this results in the addition of five extra wires to the USB cable and the connector. One differential pair is used for transmit, one pair is used for receive, and the remaining wire is for ground. USB 3.0 utilizes dual simplex data transfer, where transmit and receive pairs are separate and the effective throughput is 20 times that of USB 2.0 when transmitting and receiving data.

Power Efficiency With Interrupt-Driven Protocol

Power efficiency is the second key enhancement in the USB 3.0 specification. Power-hungry peripherals often need a dedicated power connection in addition to a USB 2.0 connection. USB 2.0 provides only 100 mA in a low-power state versus USB 3.0’s 150 mA, which is 50% more. For a configured device (an active device), USB 2.0 supplies up to 500 mA versus USB 3.0’s 900 mA, which is 80% more and enables power-hungry devices to charge quickly using only bus power.

Considerable power savings come from replacing USB 2.0’s continuous-polling feature with an interrupt-driven protocol. In USB 2.0, the host continuously polls every connected PC peripheral if it has data to transmit to the host. For example, if a USB 2.0 hard drive and printer are connected to a PC, data sent to the hard drive also is sent to the printer. USB 3.0 eliminates the need for broadcast packets. Data is transmitted only to the device that needs it.

In USB 3.0, the host or the device can initiate a power-saving mode. An idle USB 3.0 device will not drain power from the computer, but will go to a power-saving state. These features, combined with updated power management features (idle, sleep, and suspend states) at the link and device levels, allow USB 3.0 to support a tenfold performance improvement over USB 2.0, with just a twofold increase in power.

USB 3.0 IP Selection Challenges

The architectural enhancements defined by the USB 3.0 protocol make the challenge of selecting IP for a given application complex and substantial. For example, the new power management and performance improvement features influence the IP design and test. Therefore, selecting USB 3.0 IP that implements these functionalities in a robust and efficient manner is critical to developing a standard-compliant USB 3.0 SoC.

USB 3.0 can be used in many volume applications (Fig. 1). Selecting IP that is proven to support these applications can be difficult. For instance, modifying the USB 3.0 core to match the end application and integrating it into the SoC is challenging and time-consuming. Getting the controller and the PHY IP to interoperate and provide a 100% compliant and fully integrated solution is another challenge. Ensuring that the USB 3.0 PHY has sufficient performance margins across process, voltage, and temperature variations (PVT) while maintaining signal integrity and minimizing electromagnetic/radio-frequency interference (EMI/RFI) emissions across the range of operations is a third challenge.

1. Reconfigurable USB 3.0 IP can be used in multiple product SoCs.

Furthermore, availability of device driver stacks is a key criterion. New driver stacks are required to handle the faster USB 3.0 speeds, and simply extending USB 2.0 architectures to support USB 3.0 would never reach USB 3.0 throughput. Finally, stringent USB-IF certification demands rigorous simulation and FPGA validation before silicon implementation. Universality of the USB protocol requires hosts to be tested with hundreds of USB 2.0 devices and available USB 3.0 devices. These tasks can take many engineering months for successful completion.

High quality, certified controller and PHY IP cores are needed to address these complexities and meet the SoC time-to-market windows. Successful SoC designers will consider all these factors and implement a robust, flexible, and reusable USB 3.0 solution.

Seven Requirements For Reusable USB 3.0 IP

There are seven technical requirements for choosing a standard-compliant USB 3.0 controller IP and PHY.

1. Flexible USB 3.0 Controller IP

The USB 3.0 controller IP designed for reuse should implement the functions defined in the protocol specification to support all application models. The controller IP then must be configurable as a device, a host, or both (dual-role).

Figure 2 shows the typical connectivity of the controller core to the PHY cores, memory, and SoC. It has two PHY interfaces: UTMI+/ULPI for USB 2.0 PHY connectivity and PIPE3 for USB 3.0 PHY communication. To support the USB 3.0 throughput of 5 Gbits/s, the system interface should be a high-performance industry-standard interface such as AXI. The interface bus widths should be configurable to match the operational mode. Some designs may use 32 bits today, but designs have moved to a 64- or 128-bit interface to ensure USB 3.0 speeds can be met.

2. The USB 3.0 controller core connects to the PHY cores, memory, and SoC.

A memory management system that can handle USB 3.0 throughput speeds of 5 Gbits/s is critical to maximizing performance for USB 3.0 IP. Since the reusable IP will be used in several functional modes (host, device, and dual-role), memory sizes and types (SPRAM or DPRAM) and clocking speeds should be selectable to match the end-application needs.

The buffer management scheme should take clocking speeds, memory types, and system interfaces into account and define a low-latency memory system that can sustain the 5-Gbit/s throughput. In addition to hardcore configurability, the memory resource allocation must be dynamic. For example, the endpoint mode needs to ensure the FIFO buffers are appropriately allocated so the data is fetched to meet the USB 3.0 turnaround times.

2. Robust USB 3.0 PHY IP

The USB 3.0 PHY is a highly complex mixed-signal IP that needs to support 5-Gbit/s data rates with maximum signal integrity. It should be a compact design and provide performance margins to operate under worst-case PVT variations. Also, it should be easily integrated with the controller and the rest of the SoC and be proven in a wide range of foundry processes.

The USB 3.0 PHY has a line interface comprising a four-wire (two transmit and two receive) connection to support the USB 3.0 full-duplex mode (Fig. 3). It uses a PIPE3 interface to connect to the USB 3.0 controller, and it transmits and receives 480-Mbit/s data in USB 2.0 mode and 5-Gbit/s data in the USB 3.0 mode. On the receive side, the PHY performs data recovery, alignment, decoding, de-serialization, and adaptive equalization functions. On the transmit side, it serializes and sends data.

3. The USB 3.0 PHY’s line interface comprises a four-wire connection to support the USB 3.0 full-duplex mode.

One of the mandatory features to support the USB 3.0 protocol is spread-spectrum clock (SSC) generation and absorption. This clocking scheme reduces the EMI/RFI emissions by dithering the system clock and spreading the energy across the spectrum to reduce energy peaks. The PHY should provide an option to use a fixed-frequency reference clock. Also, it should be able to generate the modulated clock internally. It should handle a wide range of input clock frequencies to generate high-speed clocks for data transmission in all the modes. A single input reference clock is desirable for ease of use.

These features make the PHY clocking architecture and test scheme more complex. However, they also simplify the IP integration and clock-routing tasks at the SoC level, which makes them important for successful PHY IP implementation.

At USB 3.0 performance levels, signal integrity is a significant issue. The adaptive RX equalization function should be designed to adjust the receiver automatically to recover the 5-Gbit/s incoming data for channel lengths ranging from several centimeters to 3 meters. The PHY design should carefully match the controller design to prevent the false detection of electrical-idle on the data lines or low-frequency periodic signaling (LFPS) as defined in the PIPE3 specification.

Similar to the controller, the PHY core needs to support the USB 3.0 compliant power management schemes (U0, U1, U2, and U3). The power-down modes vary based on the operating mode, i.e., SuperSpeed, Hi-Speed, Full-Speed, or On-the-Go (OTG) modes. The validation of the power-down functionality is complex but necessary for proper interoperability between the controller and PHY.

The USB 3.0 PHY must be available in the foundry processes that meet the application’s criteria such as wafer price, area and power. Since multiple applications use USB 3.0, demand for the PHY ranges from low-cost 130-nm to state-of-the-art 28-nm processes. As a result, multiple USB 3.0 PHY architectures based on 3.3-V I/O, 2.5-V I/O and 1.8-V I/O devices are required depending on the process geometry.

3. USB 3.0 IP Test And Testability Implementation

Silicon testing is an expensive but important step in taking a SoC to production. The test requirements for the USB 3.0 IP solution are stringent due to the protocol complexity, operation speeds, and memory requirements. However, since USB 3.0 is used in many price-sensitive applications, silicon test time needs to be very short and cost-effective.

The controller and the PHY IP need to provide test features such as built-in test (BIST), internal scan, and JTAG for boundary scan. In addition, programmable loopback options to loop the transmit data back to the receive data path from several points in the data paths need to be implemented.

The digital IP needs to implement JTAG per the IEEE 1149.1 specification, and the test access port (TAP) controller should have easy access to all the hardware resources including the registers and the RAM buffers. The PHY BIST features should include pseudorandom binary sequence (PRBS) support for bit error testing. The link integrity tests should provide flexible program parameters to validate channel performance margin.

4. Thorough, Reusable Verification Flow

A reusable IP verification system should include a standalone test environment for the controller and the PHY. In addition, it should cover verification of the USB 3.0 controller and the PHY cores as an integrated USB solution. To ensure interoperability and performance, a thorough verification strategy to test the USB 3.0 IP is required. The verification environment and functional coverage plan must cover all the IP configurations and provide 100% coverage for compliance tests.

A PHY verification system needs to simulate the PHY’s analog functions as well as signal integrity and channel loss. The typical PHY simulator implements a four-state simulation scheme, but it should also effectively simulate the voltage and current changes on the signal-lines over time. Extensive signal integrity simulation using precise HSPICE models of TX and RX channels, including analog front ends and receive equalization, is necessary.

5. FPGA Prototyping And Hardware Validation

Design validation using FPGA systems is an integral part of the SoC design methodology. Critical design issues can be identified before tape-out, minimizing risk and time-to-market. Since USB 3.0 requires extensive software development to support the various device classes, FPGA prototyping enables concurrent development of USB 3.0 firmware.

When using an FPGA validation platform, resets and clocks can be sourced from the on-board clocking system to match the operational mode. The validation should be cycle-accurate and support all types of USB 3.0 data transfers at speed. Real-world testing at USB 3.0 speeds helps to verify the architecture, such as memory management and interoperability tests for USB 3.0 standard compliance. Lastly, an FPGA validation platform also can be used for USB-IF certification of a prototype design.

6. Complete Device Drivers And Programming Models

Device drivers play a critical role in supporting USB applications and are highly complex due to the diversity of applications and the combinations of functionality. Device drivers that interface between the hardware components, i.e., the controller IP and the application-specific peripheral driver stack, are a key deliverable for USB IP.

Device drivers program the core’s registers. Its features and functionality correspond to the IP configuration mode, i.e., device, host, or dual-role. For example, in device mode, the device driver should support device-initiated disconnects by dynamically mapping physical endpoints to logical endpoints.

When operating in the USB 3.0 mode, the device driver needs to support the stream protocol and implement a different class of devices. In USB 3.0 host mode, the host functionality should be implemented according the xHCI specification where both USB 2.0 and USB 3.0 operation can be simultaneously active to support USB 2.0 and USB 3.0 devices concurrently.

In all configurations, the device driver should automatically build descriptors and a control buffer management structure. It needs to implement power management methods per the USB 3.0 specification and other IP-specific power management schemes. It also should support bulk and isochronous type data transfers by managing command queuing, stream support, and out-of-order packet management.

7. USB-IF Certification

The USB Implementers Forum (USB-IF) manages all aspects of the USB specification, including overseeing certification testing. While certification applies primarily to end products, USB 3.0 digital and PHY IP also can be certified as part of a design.

USB-IF certification is a critical and essential component of quality USB products. Through rigorous software and electrical testing, certification verifies compatibility with other USB devices. USB 3.0 certification includes protocol, link, physical, and electrical compliance tests.

Interoperability tests include verifying the attach/detach functionality and various lower management modes such as suspend, hibernate, and hybrid sleep modes and warm and cold boot. A USB 3.0 host can be connected to a USB-IF specified sample of devices to test for USB 2.0 compatibility. Certification is an extensive process that typically takes about three months.

USB 3.0 IP Selection

When selecting a USB 3.0 controller and PHY IP, the seven technical requirements for reusable IP are not the only considerations. SoC designers must also consider the additional features and functionality that the provider can bring to their design.

DesignWare USB 3.0 IP from Synopsys is a complete, USB-certified solution consisting of digital controller IP, PHY IP, and production-quality device drivers. The IP can be instantiated on the Synopsys HAPS FPGA-based prototyping solution and verified with fully interoperable verification IP. The digital IP supports all modes of operation (device, host and dual-role), and these modes are easily configurable.

The DesignWare USB 3.0 PHY is a compact and power-efficient design. It provides flexibility to adapt to diverse applications and SoC implementations. Supporting a wide range of metal stacks and package types, the DesignWare USB 3.0 PHY IP is available today in popular silicon proven processes ranging from 130 nm to 28 nm.

The DesignWare USB 3.0 IP is a standard-compliant, feature-rich and easy-to-use IP solution that follows advanced design methodologies and stringent test and certification processes to enable a low-risk implementation of USB 3.0 in an SoC.

Summary

It is critical to select a silicon-proven and certified USB 3.0 IP that can be reused for multiple applications. Chief IP requirements include robust implementations of USB 3.0 features, backward compatibility to USB 2.0, test, and certification. The digital core should be easily configurable to support multiple operational modes such as device and host, and the PHY should be compact and available in different process technologies.

Also, the PHY and the controller should be verified as a complete solution in various configurations. The cores and the test environment must render themselves for easy integration in the SoC, and the IP supplier should include hardware validation using FPGA prototyping to complement simulations and to enable concurrent software development. The IP vendor needs to provide a complete device driver stack that can interact with customer’s application software as well. Finally, USB-IF certification is a must.

Choosing an IP solution such as the DesignWare USB 3.0 controller and PHY will enable SoC designers to develop a high-quality USB 3.0 silicon solution to meet growing market demands in a timely manner.