Catalyst Semiconductor has been awarded a U.S. patent (number 6,518,737) on its low dropout (LDO) linear voltage regulator design. The new circuit technique enhances Catalyst’s capability to incorporate its programmable EEPROM technology and mixed-signal design into system level ICs.
“This patent grant is an important milestone in Catalyst’s movement toward system-level ICs that combine our extensive EEPROM capability with mixed-signal circuits,” said Barry Wiley, vice president of marketing for Catalyst Semiconductor. “We believe exploiting this capability will allow us to make key contributions to our existing mobile communication, automotive, and consumer electronic customer base.”
The patent covers an LDO linear regulator with non-Miller frequency compensation. Optimum frequency compensation and transient response are obtained by using wideband, low-power operational transconductance amplifiers (OTAs). In contrast to previous approaches, requiring tightly specified equivalent series resistance (ESR) for the external capacitor, the patented solution imposes no lower ESR limit. An LDO using a low ESR load capacitor will exhibit superior transient response with less undershoot or overshoot. The transient response of the patented LDO very nearly resembles the response of a single-pole system.
