Embedded systems are everywhere, or hadn't you noticed? The organizers of the Design Automation Conference (DAC) certainly have. As a result, this year's 38th DAC (June 18-22) will take on a decidedly embedded flavor as the EDA industry's annual shindig rolls into the Las Vegas Convention Center.
DAC continues to grow in size and gain more influence on the EDA industry. Some 17,000 attendees are expected at this year's conference with a record 260 exhibitors of EDA tools, intellectual property (IP), and silicon to keep them busy on the show floor. The technical sessions will feature 160 paper presentations, panel sessions, and tutorials on subjects from integration and verification of IP to FPGAs versus ASICs, to analog design flows. DAC offers something for everyone interested in EDA.
The overall technical program in-cludes 50 sessions that home in on such topics as supply-chain management, verification, hardware description languages, IP integration, logic synthesis, and analog and mixed-signal hardware design. Nine special sessions within the program feature invited presentations by leading academic figures and engineers. Topics for these segments include "Nanometer Futures," in which presenters will explore the cost and quality issues related to consistent production of working nanometer silicon. Another special program of interest is "Closing the Gap Between ASIC and Custom Design Examples." This segment will show examples of how circuits designed in an ASIC (RTL synthesis) methodology are bridging the performance gap with circuits designed in custom methodologies.
Other special sessions will look at topics like design for subwavelength manufacturability, configurable computing, verification, inductance issues in high-speed design, visualization and animation in VLSI design, on-chip communication architectures, and the factors driving EDA innovation today. All of these sessions promise to be forward-looking and engaging explorations of topics that will interest engineers for years to come.
Keynote addresses are always a DAC highlight. On June 19, Henry Samueli, co-chairman and chief technical officer of Broadcom Corp., will deliver this year's opening keynote. Samueli's address, entitled "Designing in the New Millennium: It's Even Harder Than We Thought," will cover the challenges facing the design community in the development of very complex SoCs and why a comprehensive EDA strategy is key to rapid time-to-market.
A second keynote address will be given on June 21 by Willem P. "Wim" Roelandts, president and CEO of Xilinx Inc. In his address, "FPGAs Enter The Mainstream," Roelandts intends to provide attendees a glimpse of some FPGA innovations on the horizon, such as embedded processors, high-level language support, remotely configurable hardware, and fast serial I/Os.
In addition to the full slate of technical sessions, there will be six full-day tutorials to choose from on June 22. Topics include "Design-for-Test Techniques for SoC Design," "CAD Tools for Mixed-Signal and RF ICs," and "Low-Power Tools and Methodologies for the ASIC Industry." There will be an interactive tutorial on the fundamentals of signal integrity for high-speed/high-density design. Other tutorials will cover architectures and CAD tools for field-programmable devices and design-to-manufacturing interfaces for ultra-deep-submicron designs.
Plus, two workshops are offered. One, the Workshop for Women in Design Automation, titled "Smart Risk Taking = Innovation," will run from 9 a.m. to 4 p.m. on June 17. It will feature prominent EDA industry leaders and a discussion on strategies for establishing workplace environments that encourage and reward smart risk-taking to improve product development and promote success. Lynn LeBlanc, senior vice president of customer advocacy at Cadence Design Systems, will deliver a keynote address. Also during this event, the second annual Marie Pistilli Women in EDA Achievement Award will be presented to an individual recognized for helping to advance women in the EDA field.
The Workshop for Women, a returning event at DAC, is an example of how the conference strives to be inclusive and to foster an atmosphere of growth within the EDA community. This year's Interoperability Workshop, also returning from previous years, will run from noon to 5 p.m. on June 17. The workshop shows the EDA community reaching out to the silicon world as leading engineers from top design companies discuss how the EDA industry can keep pace with the rapid gains in semiconductor technology through the development of a standard application programming interface for sharing design information.
Over the years, DAC's organizers have made efforts to recognize industry trends and expand the conference and exhibits by giving groups of exhibitors a home within the show. For example, in past years, DAC featured its Silicon Village, a self-contained area on the show floor for IC and IP providers. This tactic proved successful enough that this year's show won't have a Silicon Village. Assimilated into the whole of DAC proper, the IC and IP vendors will be dispersed throughout the show floor.
DAC's organizers now have turned their sights not to a product-specific area but to a broader target, the embedded-systems world, in a new effort to enlarge the conference and establish a beachhead. According DAC general chair Jan Rabaey, of U.C. Berkeley, embedded systems are the next frontier for DAC. "System-on-a-chip (SoC) design is rapidly becoming a dominant area of the design automation industry," Rabaey said. "Thus, the 38th DAC is dedicating a significant share of its program to this area while still maintaining a wide and diverse technical offering in all aspects of the design industry."
Embedded Showcase Added In emulation of the Silicon Village of years gone by, this year's exhibit floor will house an Embedded Systems Showcase to highlight the latest tools and methodologies for automating the design of embedded systems and components. It will offer a forum for vendors and designers to exchange ideas and opinions related to tools and methodologies for designing embedded systems. Featured product areas within the Embedded Systems Showcase include hardware (SoCs, IP reuse, and on-chip buses), software (run-time schedulers, middleware, and compilers), hardware/software co-design (specification languages, interfaces, integration, partitioning, and synthesis), validation (debug, performance estimation and analysis, and co-simulation), and applications (application-architecture interaction, networked and distributed systems, and multimedia systems).A highlight of DAC for those interested in embedded-system design will be a plenary panel entitled "Embedded System Design: The Real Story." Chaired by Alberto Sangiovanni-Vincentelli of U.C. Berkeley and a founder of Cadence Design Systems and Synopsys, this panel will take place on June 20 at 10:30 a.m.
Embedded-system designers face a wide range of challenges, with multiple and conflicting requirements related to cost, performance, functionality, safety, and time-to-market. In the face of these requirements, much restructuring has occurred in terms of how design is actually carried out. Both design and manufacturing are increasingly outsourced, making the interfaces between system houses, IP providers, semiconductor vendors, and manufacturing companies the pivotal points in the process of bringing embedded systems to market.
The participants in the panel will address issues associated with critical markets now dependent on embedded systems, namely automotive, cellular, and consumer electronics. They'll also explore the challenges and trends related to embedded software design. Finally, platform-based design will be examined as an effective means of reducing the risk and complexity of the design process as well as sustaining the electronics supply chain. (See "SoC Design Methods Evolve To Meet The Need For Speed," electronic design, April 2, 2001, p. 79.)
A number of technical sessions are likely to interest embedded-system engineers as well. As in past years, the program is split into two tracks. One, the Design Tools track, focuses on new techniques for enhancing the performance and capabilities of EDA tools. The other is the Design Methods track, which looks at the insights gained from applying EDA tools to real-world system designs.
Aside from the plenary panel discussed earlier, eight more sessions within the technical program directly target embedded designers. Each one focuses on a particular area of interest.
System-Level Configurability Session 3, "System-Level Configurability: Bus Interface and Processor Design," will present technologies that enable and exploit system-level configurability. The session will focus on system bus networks, interfaces, and configurable processors. One paper offers a novel high-performance protocol for system buses called Lotterybus. Another addresses the design of interfaces that enable multiclock and hybrid synchronous/asynchronous systems.Designers interested in Bluetooth will want to catch Session 17, a special session titled "Dissecting an Embedded System: Lessons from Bluetooth." In it, the design process and methodology of a leading-edge Bluetooth chip set will be presented and analyzed. The Bluetooth standard carries with it rigorous specifications and high complexity, which make advanced design verification and test techniques a priority. Both topics will be discussed in this session.
DSPs are an increasingly popular element of embedded-system designs, and with DSPs come a variety of issues associated with system memory. Session 23, "Memory Optimization Techniques for DSP Processors," will squarely address these issues. One paper examines algorithms that can help designers exploit multiword memory transfers, while another shows how to reduce address register changes for common DSPs. Two others discuss ways to automatically reduce the total memory needed by applications.
Real-time embedded-system design presents a number of challenges above and beyond those of other embedded applications. Session 28, "Energy- and Flexibility-Driven Scheduling," will look at several applications of static scheduling in the context of real-time embedded systems. There will be a discussion on a voltage scheduling algorithm based on static timing analysis that controls the supply voltage to exploit all available slack. Another paper shows how to account for battery characterization when optimally scheduling tasks in a real-time system.
The third paper in Session 28 is a candidate for one of DAC's annual Best Paper awards. Authored by Paul Pop and others from Linkoping University in Sweden and titled "An Approach to Incremental Design of Distributed Embedded Systems," it describes how to start with an existing system running a given set of applications, and how to implement new functionality without disturbing the already running applications. Moreover, the paper shows how to add functions in such a way that there's a good chance for further changes to the system with little difficulty. The authors examine the mapping and scheduling problems that ensue in such a scenario in the context of a realistic communications model based on a TDMA protocol.
Embedded-system designers are becoming increasingly interested in SoCs and how to adopt or customize them for specific applications. Session 32, "Application-Specific Customization for Systems-on-a-Chip," will examine this topic in detail. There's a paper looking at how to tailor processor architectures for media applications, while another explores a family of multiprocessor architectures for communications problems.
In the course of designing an embedded system, there are many system-level decisions to make. Session 37, "Analysis and Implementation for Embedded Systems," will feature tools and design flows for system design, performance tradeoffs, and power estimation.
Record Number Of Exhibitors Of course, a technical conference alone doesn't make a trade show. This year's DAC will have a record number of exhibitors, many of whom will premiere new products for the first time anywhere. When you need a change of pace, head out onto the show floor and into the demo suites. There you will be able to glimpse numerous new EDA products, including the following:Signal-integrity analysis: With process geometries shrinking and clock frequencies rising, it's critical for SoC designers to address signal-integrity problems so they meet timing closure. To meet this crucial need, Synopsys will show its new PrimeTime Signal Integrity (PrimeTime-SI) product, intended to detect and resolve crosstalk on 0.18-µm and below SoC designs (Fig. 1). It includes an integrated delay calculation engine that accurately models and computes the signal timing deviation (speedup or slowdown of nets) due to crosstalk. Customer evaluations show that PrimeTime-SI's timing estimates correlated to between 5% and 10% of Spice on most nets.
ASIC synthesis: With most ASIC designs running between 500,000 and 1 million gates (according to research by Collett International), productivity in ASIC synthesis has become a major hurdle in the time-to-market race. Synplicity Inc. is unveiling its Synplify ASIC tool, billed as the industry's first timing-driven ASIC synthesis product optimized to improve productivity for most ASIC designers. The software is said to offer runtimes of up to 10 times faster than traditional synthesis products. It also brings a top-down design methodology to the table. This methodology enables designers to perform timing-driven synthesis on designs of up to 2 million gates in a single operation, supporting matching hierarchy and constraints in synthesis and place-and-route steps.
Speed begets productivity, and the Synplify ASIC software uses Synplicity's Behavior Extracting Synthesis Technology algorithms and Synthesis Constraint Optimization Environment to greatly accelerate the synthesis of ASICs. Productivity is enhanced too by the elimination of the need for complex scripts and commands. The company believes that users can become proficient in a single day.
SoC routing: Routing is one of the most crucial parts of physical design. Now that more SoCs are being implemented in 0.13-µm processes, existing physical design tools are in danger of running out of steam. Plato Design Systems, a recent startup, hopes to have the answer in its NanoRoute tool.
The scalable router is said to be based on the industry's first graph-based routing technology. It's claimed to deliver more than a tenfold speed increase compared to the fastest grid-based routers. At the same time, NanoRoute offers the flexibility of gridless routers. Designers can use a single router for both block-level and full-chip-level routing. Additionally, the tool is capable of parallel routing on multi-CPU workstations for runtime speed and capacity increases that are commensurate with the number of CPUs.
Wireless SoC design: With the wireless market booming, designers seek tools that allow them to focus on their core competencies rather than on the issues related to the design flow itself. At DAC, Cadence Design Systems will demonstrate a wireless SoC design flow that incorporates RF and DSP design, platform-based design, optimization and verification, and datapath synthesis. The flow consists of a number of point tools, including Signal Processing Worksystem (SPW), Spectre RF simulator, Virtual Component Co-Design (VCC), NC-Sim mixed-language event simulator, Ambit BuildGates synthesis tool, and Quickturn verification systems (Fig. 2).
Front-end SoC design flow: In some approaches to a front-end SoC design, the tools force designers to learn physical layout. Tera Systems' TeraForm 2001.1 RTL design planning tool enables designers to focus on register-transfer-level (RTL) design creation and optimization. Resultant designs can then be handed off to a physical implementation team with a better starting point for existing gate-level synthesis and layout tools.
The 2001.1 release of TeraForm offers two new package alternatives: TeraForm-VP for RTL design exploration and TeraForm-EX for RTL handoff to logic synthesis and physical layout.
Analog SoC design tools: For designers looking to incorporate analog-to-digital converters (ADCs) within SoCs, two products from Fluence Technology will help. One, ADCBIST, enables users to quickly implement a built-in self-test (BIST) methodology for at-speed testing of ADCs in complex SoCs. Another, ADCBIST Developer, allows users to determine BIST requirements and simulate performance of ADCs before first silicon.
Verification: Forte Design Systems will weigh in at DAC with a new version of its QuickBench tool. The test-bench automation software offers a flexible environment that supports multiple languages, including C/C++ and RAVE, which is Forte's proprietary verification productivity language. The company will show a new version of its Cynthesizer C++ synthesis tool as well.
Also on the verification front, TransEDA plans to show a new system-level verification solution for ASIC, FPGA, and SoC designers. The product will integrate verification IP and system-level test-bench automation for verification of custom designs in a realistic environment.
Web-based design environments: A trend that has emerged over the last few years, coincident with the rise of the Internet, has been EDA tools and solutions that foster online collaboration between geographically dispersed design-team members. At DAC, Innoveda Inc. will roll out its DxDesigner, a Web-based application that forms the gateway linking computer-aided engineering and team-based design collaboration. The tool combines four key process technologies: a component information system; design entry and sharing; simulation and planning; and enterprise connectivity. It enables team members to coordinate their efforts and use a centralized, corporate-approved parts library. It also relies on hierarchical design techniques to enable reuse of common or standard subsystems in future designs.
With both its top-notch technical program and its leading-edge exhibits, the 38th annual Design Automation Conference has more than earned its reputation as one of the premier gatherings for the electronics OEM industry.
