The growth in high-performance computing and AI in advanced chip architectures is creating issues when it comes to intra-chip data management, especially as they migrate to chiplet-based topologies. Addressing this chip-level issue, Avicena announced its scalable LightBundle chiplet interconnect solution. It offers ultra-high-density die-to-die connections with a multi-Tb/s/mm shoreline bandwidth density at sub-pJ/bit energy efficiency.
In this podcast we talk to Bardia Pezeshki, founder and CEO of Avicena, about the issues of intra-chip data management and his company’s solution.
