·What are some differences between RISC-V core IP?
·What’s in the MIPS P8700 RISC-V core IP?
RISC-V is just an instruction set definition, albeit one that can be incrementally defined and spans functionality from an integer-based system to one that sports floating-point, virtual-machine, and vector extensions. Things get more interesting when looking at the implementations of a RISC-V core. Different implementations can offer features from multiple execution units to out-of-order execution.
I talked with Sameer Wasson, CEO at MIPS, about the company’s approach to RISC-V and how its latest core, the MIPS P8700 RISC-V core, compares to the competition. We discuss issues such as targeting safety standards like ISO 26262 and ASIL D that are utilized by the automotive industry. The new core was shown at the Consumer Electronics Show.
