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    Connector-System Density and Signal Integrity Hold Keys to PCIe 5 Success

    Oct. 5, 2021
    Optimization of PCIe connector systems and cable jumper assemblies for height, PCB density, robustness, and signal integrity enables implementation of PCIe 5, 32-Gbps NRZ data rates.

    As server/storage system architects design high-speed channels that carry signals from one side of a system to the other, they face obstacles that become increasingly challenging to overcome at higher frequencies. They also must also evaluate density requirements to minimize PCB real estate while facilitating thermal management. Version 5 of the Peripheral Component Interconnect Express (PCIe 5) bus standard paves the way for next-generation solutions that maximize system performance with respect to signal integrity and density.

    Download this white paper to learn more about PCIe 5—and how state-of-the-art connector and cable assemblies enable this technology.

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    Avnet and Molex

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