Speed up early design rule exploration & physical verification

Running sign-off DRC during early design iterations not only results in long runtimes, but also huge numbers of errors, many of which are irrelevant. Today, efficient early stage IC design verification functionality allows designers to run a selective DRC subset that ensures sufficient coverage to detect valid and critical early design issues. Designers can “gray box” unfinished blocks, checking only their interface region to capture interface violations. Post-processing and waiving of output results facilitates faster debugging and optimized fixing.