By Srinivas Velivala
Building a road is a multi-stage process. You must select the route, remove any obstructions, and level the ground before you can apply the paving. Building an integrated-circuit (IC) chip is much the same. Design teams use place-and-route (P&R) tools to implement the layout, design-rule checking (DRC) to remove construction obstacles (errors), and design for manufacturing (DFM) optimization to maximize manufacturability and performance. Of course, that’s a highly simplified (but generally accurate) view of both processes.
The challenge inherent in both is to achieve the desired results in the minimum amount of time using the smallest amount of resources possible. Overcoming that challenge often means finding new and better ways to complete the steps that make up the overall process.
P&R tools perform an automated implementation of the design description in RTL. That is, they create a physical layout that turns the designer’s proposed functionality into interconnect, devices, layers, and so on. The P&R engineers must then evaluate that layout against the design rules using DRC to find and fix any errors.
Foundries create the design rules for each process. At each new node, the number of design rules increase, and the complexity of each rule increases as well. Years ago, in an attempt to simplify and speed up the DRC process, electronic design automation (EDA) companies that provide P&R tools started building in a basic set of DRC checks. P&R engineers run this native P&R DRC within the P&R tool to find and fix a large percentage of the DRC errors in a layout.
However, this native P&R DRC functionality wasn’t designed or intended to replace the signoff DRC verification provided by tools like the Calibre nmDRC platform from Siemens EDA. Those signoff DRC tools work with DRC rule decks that cover the complete set of design rules for a node, and have been qualified by the foundry to notify a design is free of errors that would impact its manufacturability.
When the P&R engineers reach the limits of what the P&R DRC can do, they must run signoff DRC against the layout to find and fix those errors the P&R DRC can’t handle. That means merging P&R and IP data into a single database, streaming that database out to GDSII/OASIS, performing a batch signoff DRC run, reviewing and debugging the errors, and applying the fixes. Oh, and then doing the whole thing over (and over, and over) again to confirm the fixes.
Since both streamouts and batch DRC can be quite time-consuming and resource-intensive, these iterations can gobble up precious schedule time, as well as both human and compute resources. Sounds like this is the point where you remove the obstructions from your roadway...
That’s just what the EDA companies did. In the last few years, innovative functionality has been introduced to enable P&R engineers to access signoff-quality DRC from their P&R environment. No streamouts, no batch DRC runs. We’ll use the Calibre RealTime Digital interface from Siemens EDA to show you one example of how this functionality works.
The Calibre RealTime Digital interface is integrated with all major P&R tools to provide direct calls to Calibre analysis engines running foundry-qualified signoff Calibre rule decks (Fig. 1). These Calibre engines perform fast, incremental checking in the vicinity of the shapes being edited, resulting in nearly instantaneous feedback on design-rule violations and recommended rule compliance. This immediate feedback within the P&R tool enables P&R engineers to implement targeted, on-demand signoff DRC and verify fixes without the need for full batch DRC iterations. And, because the Calibre verification is transparently implemented, there is little to no learning curve.
The Calibre RealTime Digital interface eliminates any gaps between the P&R tool’s built-in design rules and the foundry-qualified Calibre rule deck. Because Calibre RealTime Digital can perform all checks that are able to be run with the Calibre nmDRC platform, including recommended rules, pattern matching, equation- based DRC, preferred metal direction rules, and multi-patterning, P&R engineers can now quickly find and resolve complex errors and implement layout optimizations, such as:
- Multi-patterning errors
- Spacing errors in high-density areas
- Via swaps
- Functional/timing signal shorts
- Interface errors
- Signal electromigration (EM) errors
- Re-tapeout checks
While the ability to perform these checks and optimizations within the P&R tool provides a significant and immediate improvement in the design and verification flow, there are other benefits to on-demand signoff-quality DRC within the P&R process.
Often multiple fix options are available for a DRC error. With the time limitations imposed by the traditional batch DRC process, engineers typically implement the easiest or most obvious fix, even if that fix is not the most optimal for achieving the design’s power, performance, and area (PPA) goals.
With immediate signoff-quality DRC feedback, engineers can quickly perform a “what-if” analysis, running multiple fixes to determine the optimum fix for the design. For DFM recommended rules, they can recheck DFM scores after each optimization to determine if they are near or have achieved their target DFM score.
Every new process node brings with it new and revised design rules. Rather than enduring the usual tedious reviews and interpretations of these rules, designers can simply use the Calibre RealTime Digital interface to run a rule on a layout and see the impact immediately. By experiencing the effects firsthand, engineers can quickly see and understand the parameters and application of a rule. In today’s fast-moving markets, getting your design through production as quickly as possible can provide a significant competitive advantage.
With access to on-demand signoff-quality DRC in the P&R environment, design teams are now able to accelerate their DRC closure, saving weeks in their tapeout schedules, while minimizing both human and compute resource usage. At the same time, the correct-by-construction approach provides design companies with confidence that their high-performance designs are fully optimized for both PPA and manufacturing. The road to success just got a little smoother.
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