ADC Function Based on PWM Technique

In this implementation of a proposed PWM converter approach, the two inputs to comparator U1 are the sawtooth waveform from an arbitrary waveform generator and the dc input from a precision voltage calibrator (Fig. 2a). The sawtooth has a negative offset to ensure that there’s a pulse when the dc input is zero; the sawtooth varies from –2 V to 10 V (12 V_P-P). The digital circuit must measure the width of the generated output PWM pulse. This circuit is implemented in a CPLD, and consists of a synchronizer, counter, sequencer, latches, and three-state buffers (Fig. 2b), and interfaces to U2, a PIC microcontroller, and the RS-232 port (U3 and Conn1) (Fig. 2c).

The PWM pulse, which is synchronized with respect to the system clock, serves as an active-high count-enable signal of the 16-bit synchronous counter. The sequencer circuit generates two signals, DRDY and LRST, after the trailing edge of the PWM pulse to latch the synchronous counter output. Then it resets the counter to restart the fresh measurement and acquire new data. After synchronizing, it uses the pulse-width ON time to enable the counter, which is clocked by a fixed 4-MHz source (derived using the clock divider as shown).

The latched output is available through buffers, which are enabled by the microcontroller and subsequently read. EN1 and EN2 are the buffer-enable signals generated by the microcontroller to read the latched counter outputs for downstream processing. When the dc input varies from 0 to 9.95 V, the pulse width is measured with the counter. The sequencer, which is implemented with simple shift register, ensures that the counter output is reset only after latching into the register.

Since the count for 0 V dc is already known (both mathematically and empirically), the result for any value from 10 mV to 9.95 V is computed by subtracting the measured counts with the zero value. The equations for the width of the PWM waveform and factors are:

• T_{W =} T_P × (|V_Neg-pk | + V_DC)/ V_P-P,

• Synchronous counter output value = T_W × T_CLK

• Float Normval = (counter output  –  count offset) × scaling factor

• Int ADCVAL = Normval – Lin factor

where:

T_W = pulse width (ms)

T_P = time period of sawtooth wave  

• V|_Neg-pk | is the peak negative voltage, taken in absolute scale

• V_DC  =  0-10 V dc input voltage   

• V_P-P = peak-to-peak voltage levels of sawtooth waveform

• T_CLK = the sampling clock to the synchronous counter

• Count offset = the counts corresponding to V_DC =  0 V

• Normval = a software variable multiplied by appropriate scaling factor

• ADCVAL = a software variable indicating the final ADC count value (in millivolts) after the linear factor correction (Lin factor).

For the proposed design, V_P-P  = 12 V, |V_Neg-pk | = 2 V, and T_P = 2 ms (500-Hz period) were chosen. This resulted in a pulse width ranging from 333 µs for V_DC =  0 V to approximately 2 ms for V_DC = 9.95 V. The corresponding counter outputs varied from 1332 (min) to 8000 (max) count, respectively, for T_CLK = 4 MHz.

The scaling factor is evaluated by the formula (8000 -1332) × scaling factor = 10 V. Here, the scaling factor worked out to be 1.5 (mV). Linear factor is evaluated after tabulating the measured value of ADCVAL for the corresponding input dc voltage and estimating the slope by curve fitting (see the table). The Lin factor was derived as ((Int)Normval × 7) mV.

The scope photos (Figs. 3 and 4) show the output pulse widths for dc inputs of 8 and 4 V, respectively. The output results for this PWM-based approach to implementing an ADC shows only minor variations compared to the expected value. The tabulated value indicates that the proposed design functions as a 10-bit ADC.

G.V.Kishore and K.Palanisami are with the Power Electronics Section, Electronics & Instrumentation Division, Indira Gandhi Centre for Atomic Research (IGCAR), Kalpakkam-603102, Tamilnadu, India.