EMC Symposium addresses channel characterization and modeling

Pittsburgh, PA—Channel characterization and modeling was a topic of interest at the EMC Symposium, held here this week. In a session Tuesday afternoon chaired by Jianmin Zhang of Cisco Systems and Ye Chunfei of Intel, presenters representing Rambus, Ohio State, Intel, Purdue, Cisco, and Missouri University of Science and Technology discussed topics including system-level jitter, IC package analysis, end-to-end measurement of high-speed link performance, full-wave solvers, crosstalk cancellation, and ASIC package design optimization.

In the first paper of the session, Dan Oh noted that at increasing I/O speeds, device jitter contributes significantly to overall timing error. Oh, who worked at the signal and power-integrity group at Rambus Inc. when he wrote the paper but who now works at Altera, explained that conventional deterministic jitter components such as inter-symbol interference and duty-cycle distortion remain relatively constant, but other uncorrelated jitter components including random jitter (RJ) and power-supply noise-induced jitter become more critical and harder to reduce. In his paper, Oh reviews the concept of jitter amplification and cancellation using a clock signal, describes a statistical link-simulation methodology that can help analyze system-level behavior, and examines the correlation between on-chip measurements and simulation results.

Signal-integrity issues related to interconnections in 3-D stacks were addressed in a paper by Yang Shao, Zhen Peng, and Jin-Fa Lee of Ohio State University's ElectroScience Lab in the Department of Electrical and Computer Engineering. Presenter Shao noted that with increasing clock frequencies and the downscaling of feature sizes, SI effects like signal delay, reflection, attenuation, dispersion, and crosstalk are becoming dominant factors limiting overall performance in high-speed systems. She also noted that power-integrity (PI) issues are presenting major difficulties because shrinking supply voltages and the finite resistivity of the many metal layers found in complex devices. To help address such issues, she presented what she called “non-conformal, non-overlapping domain decomposition methods (DMMs) for DC IR drop and AC signal-integrity (SI) analyses of high-power chip-package PCBs.” She concluded by noting that measurement results verify the analytical approach.

In another measurement-related paper, Chunfei Ye, Kai Xiao, Michael Johnston, Ricardo U Chavez Cuadras, and Xiaoning Ye of Intel introduced a measurement methodology to evaluate high-speed-I/O die-to-die link performance, where the die-to-die link extends from a transmit silicon pad to a receive silicon pad. Presenter Chunfei Ye said the authors' approach involved the use of a BERT and oscilloscope to serve as transmit and receive buffers, respectively. He noted that the methodology can be applied before silicon tape out. It can serve to de-couple silicon and interconnect system issues, provide input for new spec development, and correlate simulation and measurement results.

In other papers presented during the session, Jianfang Zhu and Dan Jiao of the Purdue University School of Electrical and Computer Engineering described a fast and accurate O(1) solution to the low-frequency breakdown problem of full-wave solvers that is applicable to general 3-D problems. Xiaoning Ye, Kai Xiao, and Raul Enriquez of the datacenter and connected system group at Intel described differential far-end crosstalk cancellation and the difficulties of implementing it on a production board. And finally, Jane Lim, Kai Soon Chow, Jianmin Zhang, Kelvin Qiu, and Rick Brooks, all of Cisco Systems Inc., and Ji Zhang  of the Missouri University of Science and Technology described ASIC Package Design Optimization for 10 Gbps and higher backplane Serdes links.

Editor's Note: Updated 10/30/2019  with link to current Program at Purdue.