Synopsys Uses AI to Ease Information Overload in Chip Design
Designing a modern chip is a complicated, three-dimensional design problem that takes years even for giants such as AMD and Intel, requiring up to thousands of engineers and hundreds of millions of dollars.
It is impossible for engineers to work out every single detail in chips by hand, so they use electronic-design-automation (EDA) tools to assist with everything from arranging components on the floorplan of a chip to verifying performance ahead of production. EDA tools create vast amounts of data that companies use to root out weaknesses in a chip's design. But it tends to be more data than engineers know what to do with.
Synopsys has introduced a big-data analytics tool that uses machine learning to make sure its customers can harness more of the data at their disposal. Called DesignDash, the new platform sifts through the data to pinpoint areas on system-on-a-chip (SoC) designs that engineers could stand to improve.
The Santa Clara, California-based company said the tool gives companies a real-time “360-degree” view of the vast dossiers of data being amassed run-to-run, design-to-design, and project-to-project during the chip development process. Evaluating it, Synopsys explained that DesignDash can uncover previously unseen insights from the data used by companies to help guide faster and more informed chip design decisions.
The company has started adding artificial-intelligence technology called DSO.ai into its flagship suite of EDA software to help human engineers nail down better chip designs faster than they could alone.
Many of the company’s rivals, including Cadence, are also investing more aggressively AI-based chip design tools to help engineers balance tradeoffs on performance, power efficiency, area, and cost in modern chips.
“The semiconductor industry needs a dramatic improvement in design process productivity,” said Sanjay Bali, VP of marketing and strategy in the silicon realization unit at Synopsys, in a statement.
Enhanced Visibility
Synopsys said DesignDash is used to pinpoint the regions in the chip design that are ripe for improvements, while the DSO.ai technology helps identify the best ways to optimize the performance, power, die area, and cost of the final design. Bali said the new software tool is unlocking the potential of the vast amounts of data collected during the chip design process and “heralding a new era in smarter chip designs.”
Optimized to run on the cloud, DesignDash leans on machine learning and data analytics to identify limitations in a chip design, pinpoint the root cause of problems, and propose potential resolutions.
DesignDash also helps improve visibility into the chip design process, giving companies real-time status updates through visualizations and interactive dashboards. This allows engineers at different stages of the chip design process and even in different locations around the world to share insights and collaborate.
Synopsys said DesignDash also complements its suite of silicon lifecycle management tools that gather data from a chip in the field and manufacturing tools in the fab. As a result, engineers can glean valuable data from the pre-silicon and post-silicon stages of a chip’s lifecycle, giving them more opportunities for data analysis.
"SoC complexity across all application niches continues to rise as more functionality and performance is required," said Karl Freund, founder and principal analyst of Cambrian-AI Research.
Using machine learning, “engineering teams now have an efficient way to share and use valuable insights that would otherwise take hours of manual work to compile or, in some cases, not be accessible.”
