In the days of large split supplies, it was relatively easy to make a good monostable multivibrator. Even 5-V single supplies posed only a moderate challenge. Making a good one-shot to run on 3.3 V is more difficult, though. The variation of CMOS thresholds limits their usefulness for precise timing. Plus, limited voltage " headroom" can make designing a good reference plus comparison circuitry difficult outside the environment of monolithic matched parts.
However, newer devices make an old job practical in a new environment. This one-shot uses a low-voltage differential-signaling (LVDS) receiver to perform an otherwise difficult comparator function.
Figure 1 shows the rudiments of this one-shot, in which A1 represents the LVDS receiver. A negative input pulse causes U1's output to fall, turning off Q1, and allowing the voltage at its emitter to fall as R1 discharges C1. At the same time, the voltage at the junction of R2 and R3 steps down.
Because the step is now lower than Q1's emitter, A1 (through U1) holds down the output later than the rise of the input pulse. When the voltage at Q1's emitter falls to the bottom of the step, the output of A1 rises, terminating the output pulse. If the voltage-division ratio of R2 and R3 is about 38%, the duration of the output pulse will approximate R1 × C1. D1 compensates the VBE of Q1. The stationary-end of C1 could be grounded, but doing so sends large transient reset currents through the power supply.
Figure 1 may be satisfactory for long durations, using slow transistors. However, short durations will require the modifications of Figure 2. Short durations require fast transistors, many of which will oscillate using their packages as resonant tanks unless losses are introduced correctly.
R1a stabilizes Q1 and limits reset current. R2a is added to R2 to compensate for the voltage drop of R1a. Because most signal diodes poorly match high-speed transistors, Q2 replaces D1. However, it can't simply be diode-connected, thus requiring R4 to prevent oscillations. The splitting of U1 into two NAND gates is convenient. It provides an inverted output, useful for stabilizing the current in Q2.
A number of other configurations of this circuit are theoretically possible, but most LVDS receivers include a "fail-safe" function that forms an implied AND gate between their inputs and outputs. Making this circuit compatible with that implied AND function eliminates many otherwise useful configurations.
Figure 3 shows an actual schematic diagram that has been simulated in Spice and prototyped. The previously unused sections of U1 generate a short input pulse at the rising edge of the input. R2a is merged into R2, and C3 is added to compensate for the stray capacitance (CS).
It's necessary for the rising edge of the step to always be faster than the ramp reset, lest wrinkles appear on the rising edge of the comparator output. The value of 11 pF for C3 is approximate, the actual value depending on layout. When the capacitive division ratio equals the resistive division ratio, the step divider output will be flat-topped, just as when we compensate scope probes.
R1a limits the speed with which this one-shot can be repetitively triggered without changing pulse width. In the prototype, R1a was able to be reduced to about 25 before nasty wrinkles got too bad on the waveforms. Adding other small resistors to Q1's terminals may allow further reductions of R1a, which ultimately shrinks reset time.
The prototype was temperature tested from 25°C to 50°C. Over this range, absolutely no variation of pulse width was observable on the 100-MHz analog scope that was used for the test. A change of 1 ns would have been plainly evident. On top of that, no wave shape changed over the tested temperature range.
Outputs may be taken as shown at U1, pin 8; at A1, pin 7; at U1, pin 11; or at all of the above, yielding both polarities of output pulse.
The values shown yielded an output pulse width of 93 ns, the theoretical duration (the time-constant R1C1, being augmented by the propagation delays of the active devices). At longer durations, the effect of these delays would be diluted. The circuit was well-behaved and could likely be pushed to a fraction of the duration tested.