Facing The Challenge Of Adding RF And Mixed-Signal IP To SoCs

As CMOS technologies scale to greater densities, the ability to design and integrate complex and sensitive mixed-signal and RF intellectual property (IP) is becoming a reality. In fact, RF and analog/mixed-signal (RF-AMS) IP content is viewed as the next great enhancement to system-on-a-chip (SoC) design. But so far, very few products using this level of integration have been announced. This article steps through several key obstacles in the path of designers trying to integrate aggressive RF-AMS IP. It gives an overview of the issues pertaining to the process design kit (PDK), design, and CAD areas.

As an example, the demanding requirements for evolving network chip complexity cause new implementation challenges. Often, designers take an evolutionary approach toward developing large network system chips. Figure 1 shows a generic flow of integration as process technology migrates. The possibilities for complex RF-AMS IP integration have become very real, especially with the advent of advanced RF-CMOS processes.¹

For networking, integrating high-speed (3- to 10-Gbit/s) custom digital serial links is a leading requirement. This definitely requires state-of-the-art design and implementation methodologies.

When discussing RF-AMS IP, it's important to define the terms, mainly because some confusion clouds this area. Some key characteristics include:

• Requirement for IP migration/targeting: Top-down design is necessary.
• Multiple feedback loops between analog and digital blocks: Chip-wide functional design and verification is very important.
• Tight constraints on floorplanning: Analog blocks need constraints.
• Numerous custom analog, digital, and standard cell digital blocks: Many are imported from different design groups or IP vendors.
• High-performance analog blocks: They are sensitive to noise and linearity requirements (wireless).

Note that although this list isn't complete or mandatory in defining RF-AMS, it is indicative of the issues that designers face.

CAD Design Flows: Figure 2 shows a challenging RF-AMS IP integration problem. At first, the design can be viewed as a distinct set of blocks—data converters, a DSP, and an RF power amp. Designers may be inclined to design these blocks independently and assume successful integration. This is the typical approach taken today, mainly due to the lack of CAD tools that handle both the digital issues (with the associated capacity issues) and the RF-AMS issues.

But inspect the design more closely and the simulation and physical-design problems should become apparent. For instance, the design has multiple simulation domains that must be cosimulated—RF (power amp), mixed-signal (data converters), and register transfer level (DSP).

Figure 3 is a high-level CAD methodology for designing analog blocks in large SoC designs. The diagram shows two CAD flows. One flow is for the SoC design (left), including the need for analog-aware capabilities throughout. The second flow represents the RF-AMS IP design (right) with complex components, such as mixed-signal simulation and handling of accurate interconnect parasitic extraction, including transmission-line modeling.² The RF-AMS IP is designed, then imported back into the SoC design flow. Some interesting points to notice in the figure are:

• The diagram reveals the need for chip-wide "mixed-signal AHDL" simulation, and then the requirement for further simulation once the IP blocks have been integrated using FastSpice simulators. Standards like Verilog-AMS and VHDL-AMS have recently emerged and are key to developing new mixed-signal simulation engines. The issue of RF cosimulation, as required in this design, hasn't yet been fully tackled in the CAD world.
• Floorplanning, sometimes called physical design planning, is automated today for designing block-based digital ASIC and SoC designs. But the integration of RF-AMS IP brings an urgent need for analog-aware constraints to be implemented in the system. Furthermore, constraints must be passable from the SoC design CAD framework to the RF-AMS IP design CAD framework—and vice versa.
• Once the RF-AMS IP has been designed, it needs to be "packaged" to produce certain views/abstracts for integration into the larger design. (Figure 3 lists these generically, and References 3 and 4 provide more specific details to RF-AMS IP integration.) IP packaging is a very significant piece of the whole design flow because it bridges the RF-AMS IP design stage to the SoC integration stage.

Parasitic Noise Issues: An analog circuit has many nodes where its performance could be highly sensitive to the noise issues in the previous stages. For example, the performance of the power amp in Figure 2 may be affected by quantization noise issues in the digital-to-analog converter (DAC). Figure 4 provides a high-level abstract view of the resistance-inductance-capacitance (RLC) parasitics that designers need to consider. (Reference 2 offers a complete background to each of these areas.) For both RF-AMS and digital designs, parasitic noise can be broken into the following categories:

• Interconnect crosstalk usually comes from the capacitive coupling between the victim net and one or more aggressor nets. But inductive coupling also is starting to show up in cutting-edge custom designs. The problem of interconnect crosstalk is getting worse with each process generation due to nonideal scaling of wires.

With each new generation, wires grow relatively narrower and taller to keep their resistance manageable. So the ratio of the coupling capacitance of a wire to its total capacitance increases every generation. Although the move from aluminum to copper can halt this deterioration for a generation, successive generations will again have to tackle the same issues. Therefore, it's becoming increasingly important for designers to account for coupling during timing analysis.

• The trend of expanding design size and power consumption while decreasing supply voltage and thus increasing current is resulting in a rise in the amount of power-grid IR drop and ground bounce on chips. This trend is critical because the IR drop and ground bounce noise margins are decreasing along with the supply voltage. Chip designers are already discovering chip failures due to power-grid issues, whether IR drop or electromigration. Because these issues relate to the number and way that components are assembled on a chip and are primarily a global phenomenon, power-grid analysis is becoming a required addition to many design flows.
• Substrate coupling occurs in many types of circuits, from small RF designs to large embedded memories. The key aspect of the problem is the flow of ac currents in the substrate. These currents are generated by (typically) fast-switching digital devices. Designs where problems most often occur include embedded data converters or memories in large ASICs.
• Interconnect inductance modeling has appeared as an important issue for critical high-speed nets in both analog and digital IP designs—as well as for chip-level interconnects. This is achieved through enhancements to the RLC interconnect extraction engines or transmission-line models. Extraction techniques allow for higher capacity, but they don't supply the high accuracy that transmission-line modeling offers.

Process Design Kits (PDKs): Implementing the front- and back-end libraries, which map to the foundry process technologies, is critical to the success of the design project. A PDK¹ should include a full suite of symbols, parameterized cells (PCells), netlisting routines, productivity utilities, application notes, and tested tool methodologies. That's in addition to the accurate device models typically demanded.

Incomplete coverage, including the lack of testing and support, means that the customer will have to develop and support the complete PDK, which affects the schedule and cost. IBM is taking an industry-leading role in developing a suite of silicon-germanium and RF-CMOS design kits to meet these requirements.

Figure 5 shows a high-frequency NFET PCell structure, with the terminals indicated. For successful design, an important requirement of the PDK is the use of substrate rings. This allows highly accurate modeling, such that a compact model can be built to very accurately represent the device performance. The tradeoff is the relatively high area and minimal flexibility of the structure. But given that a performance NFET can be very sensitive to its layout for RF applications, this is a much more acceptable approach.

Another important requirement for the PDK is implementing accurate and advanced passive devices, such as MIM capacitors, spiral inductors, and transmission lines. The lack of good passives has traditionally held back design teams trying to integrate analog circuitry in ASIC designs. It's a more difficult challenge for those looking to integrate RF IP onto SoC designs.

Using Industry Standards: Because many IP blocks can be integrated—often from different companies in the supply chain—it's becoming increasingly important to have industry standards for importing RF-AMS blocks. Clearly defined and agreed-upon guidelines mean a much better chance that all complexities of the IP will be correctly dealt with in the chip-integration phase.

The Virtual Socket Interface Alliance (VSIA) is leading the way in this area for both hardware and software issues in SoC design. The VSIA has released two specification documents, one for RF-AMS IP integration,³ and one for signal-integrity issues, both RF-AMS and digital.⁴ The alliance is actively extending this work to new CMOS process technologies.

The end goal is for the different communities—foundry, PDK, IP provider, IP integrator, EDA tools vendor, and so forth—to understand and effectively deliver on these technical challenges, both in the RF-AMS and SoC design areas. Figure 6 shows the major players in the chain and demonstrates the complex nature of this industry and its dependencies.

In summary, this article has briefly touched upon many of the challenges facing the design, CAD, and PDK communities as they try to integrate RF-AMS IP into large SoC designs. More detailed discussions on each of these areas are available, with a few highlighted in the references section. The author thanks Scott Parker and Carl Dickey at IBM, Larry Cooke of VSIA, Francois Clement and Steffen Rochel at Cadence Design Systems, and Prashant Saxena from Intel Corp. for their contributions to this article.

1. www-3.ibm.com/chips/services/foundry/offerings/
2. Signal Integrity Effects in Custom IC and ASIC Designs, edited by R. Singh, IEEE Press, Nov. 2001
3. AMS Specifications Document Version 2.0, Virtual Socket Interface Alliance, www.vsi.org
4. Signal Integrity Specifications Document Version 1.0, also at www.vsi.org