Fig 1. A typical CMOS input circuit comprises a “P” and “N” transistor. One is fully “on” for logic high, and the other is “on” for a logic low.
Fig 2. When a CMOS input pin is at logic high or low with low current, lots of current still flows between valid logic levels. This data is for the MAX5391 digital potentiometer.
Fig 3. Typical ESD protection structures for ICs protect signal and power pins with zener diodes and other signal pins with pairs of silicon diodes.
Some people may think that digital circuits are easy to design. But like most things in life, professionals with many years of experience make the jobs look easy. The circus performer effortlessly juggles many items. The concrete finisher creates a smooth surface, and a top chef creates a gourmet meal in a snap.
Isn’t digital design just stringing together some logic gates? If only life was so simple. Proper power management, power decoupling, and grounds are essential for a successful design.
Why Did I Burn My Finger?
Engineers choose CMOS/biCMOS logic to be “green” and reduce power consumption. CMOS and biCMOS only draw power on transitions, so those circuits run cool at slow speeds. So why is the board hot? First, consider how a simple CMOS circuit is complementary (N and P devices)—hence the name, complementary metal oxide semiconductor (Fig. 1). It’s ones and zeros and simple, so what could possibly go wrong?
When the CMOS circuit is approximately midway between one and zero, both the top and bottom transistors are partially on. Consequently, the faster the speed, the more transitions per second and the more power used. As long as the transitions are fast, the part does not stay in the middle position long, and everyone is happy (see the table).
Logic levels are typically specified as a percentage of the power-supply voltage. The waveform of Figure 2 is made by slowly changing the input voltage. If the application is, regrettably, at 2.6 V with a 5-V supply, it will draw 80 times more current than with the proper one and zero. In the case of a 5-V logic swing, if the signal is less than 0.7 V, it’s a safe zero. If it’s above 4.3 V, it’s a safe one.
This MAX5391 will interface 5-V logic with a 5-V supply and accommodate 3-V logic with a 3-V supply. Now suppose that someone wants to mate this part to 3-V logic in the input, but with a 5-V supply. The zero case works, but the one draws four to eight times more power than necessary. This is why the CMOS could be running hot. The proper fix is to use a logic-level translator between logic running at different voltages.
Turn-Offs And Turn-Ons
People generally enjoy people-watching. Engineers, in particular, enjoy details and what exactly the turn-ons and turn-offs that matter so much are. The issue is really about power sequencing. IC designers would like the power supplied to all pins to be applied simultaneously, or at least in a prescribed order.
System engineers know that this is nearly impossible without extraordinary effort and numerous extra circuits. Consequently, most circuits must fend for themselves and, at a minimum, not destroy themselves for the few seconds while the power supply stabilizes. Thankfully, modern parts aren’t like some early ICs that internally latched up and self-destructed if power wasn’t applied in the prescribed order.
Yet there are some circuits such as logic, ASICs, or processors that must be powered before logic-level signals are applied to their inputs. The system designer must understand why this is true, not theoretically but factually.
Most system designers with a few years experience have seen someone trying to troubleshoot a CMOS logic issue. The problem comes and goes, seemingly at random. Just when something starts to make sense, everything changes. The circuit nodes that were behaving properly suddenly are not.
Have you guessed the answer? Yes, of course! The CMOS was missing a power supply. A CMOS requires such a small amount of power that it will operate if one input pin is at a logic-high level. How does it work?
Picture a group of logic gates without VCC applied (Fig. 3). Here the group has all the VCC pins tied together on a bus. Now apply a logic high from an external, properly powered circuit to the signal pin C. The high level goes through the top electrostatic discharge (ESD) diode to the VCC bus. Now all the gates have power and appear to work—until the logic high on pin C becomes a zero or low. That section of logic then stops working until any input pin goes high.
With several input pins like this, the group appears to do silly, illogical things. This situation is not fun to troubleshoot and leads to a fundamental rule of design—always start with the basics. For instance, is it plugged in and are power and ground present at the proper voltages?
The ESD structures inside an IC are designed to protect the part before the customer mounts it on a product’s printed-circuit board (PCBs). The ESD diodes inside the ICs are limited in size. They can’t withstand system ESD events that come from external sources. Power-line surges and close lightning strikes will overwhelm the internal IC ESD diodes. There are practical limits to fixing ESD, and external ESD parts are needed on PCBs and systems.
Imagine a circuit that has a robust power source connected to pin C above. VCC is off for a prolonged time. The top ESD diode will try to power everything on the VCC rail. However, the ESD diode is tiny and might fail over time. In that case there may be a reason that VCC is removed—for example, to reduce power consumption. So, adding an external diode in parallel with the top ESD diode solves the issue. The external diode silicon or Schottky will carry the current and protect the IC.
Conclusion
The wisdom of experience hopefully allows us to design around some frustrating situations. If not, at least we can avoid some painful lessons. Attention to details is important. There are particular issues with the turn-on and turn-off times for CMOS and biCMOS ICs, and it’s possible to estimate their turn-on times and calculate a CMOS circuit’s behavior without VCC applied. Finally, a CMOS/biCMOS device can run “burning” hot if safe one and zero levels aren’t maintained. The best fix is a logic-level translator running between the different voltages.
An old proverb says, “An ounce of prevention is worth a pound of cure.” That’s certainly true in circuit design. A good working knowledge of the digital logic family in a design is the best way to ensure that the resulting circuits are reliable, stay cool, and do not use any more current than necessary. That thought up front can save a recall or revision or board spin later.